STM32G071 Peripheral Coverage

Overall: 881/4166 fields covered

ADC

0x40012400: Analog to Digital Converter instance 1

8/105 fields covered. Toggle Registers

Offset	Name	31	30	29	28	27	26	24	23	22	21	20	19	18	16	15	14	13	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR																	CCRDY		EOCAL	AWD3	AWD2	AWD1			OVR	EOS	EOC	EOSMP	ADRDY
0x4	IER																	CCRDYIE		EOCALIE	AWD3IE	AWD2IE	AWD1IE			OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x8	CR	ADCAL			ADVREGEN																					ADSTP		ADSTART	ADDIS	ADEN
0xC	CFGR1		AWDCH1CH						AWD1EN	AWD1SGL	CHSELRMOD				DISCEN	AUTOFF	WAIT	CONT	OVRMOD	EXTEN		EXTSEL			ALIGN	RES		SCANDIR	DMACFG	DMAEN
0x10	CFGR2	CKMODE		LFTRIG																	TOVS	OVSS				OVSR				OVSE
0x14	SMPR						SMPSEL									SMPSEL								SMP2				SMP1
0x20	AWD1TR					HT1														LT1
0x24	AWD2TR					HT2														LT2
0x28	CHSELR													CHSEL		CHSEL
0x28	CHSELR_1	SQ8				SQ7			SQ6				SQ5			SQ4				SQ3			SQ2				SQ1
0x2C	AWD3TR					HT3														LT3
0x40	DR															regularDATA
0xA0	AWD2CR													AWD2CH		AWD2CH
0xA4	AWD3CR													AWD3CH		AWD3CH
0xB4	CALFACT																							CALFACT
0x308	CCR							VBATEN	TSEN	VREFEN	PRESC
0x3D8	HWCFGR6				CHMAP23							CHMAP22							CHMAP21							CHMAP20
0x3DC	HWCFGR5				CHMAP16							CHMAP17							CHMAP18							CHMAP19
0x3E0	HWCFGR4				CHMAP12							CHMAP13							CHMAP14							CHMAP15
0x3E4	HWCFGR3				CHMAP8							CHMAP9							CHMAP10							CHMAP11
0x3E8	HWCFGR2				CHMAP4							CHMAP5							CHMAP6							CHMAP7
0x3EC	HWCFGR1				CHMAP0							CHMAP1							CHMAP2							CHMAP3
0x3F0	HWCFGR0																			OVS			EXTRA_AWDS				NUM_CHAN_24
0x3F4	VERR																						MAJREV				MINREV
0x3F8	IPIDR	IPID														IPID
0x3FC	SIDR	SID														SID

ISR

ADC interrupt and status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CCRDY rw		EOCAL rw		AWD3 rw	AWD2 rw	AWD1 rw			OVR rw	EOS rw	EOC rw	EOSMP rw	ADRDY rw

Toggle Fields

ADRDY

Bit 0: ADC ready flag.

EOSMP

Bit 1: ADC group regular end of sampling flag.

EOC

Bit 2: ADC group regular end of unitary conversion flag.

EOS

Bit 3: ADC group regular end of sequence conversions flag.

OVR

Bit 4: ADC group regular overrun flag.

AWD1

Bit 7: ADC analog watchdog 1 flag.

AWD2

Bit 8: ADC analog watchdog 2 flag.

AWD3

Bit 9: ADC analog watchdog 3 flag.

EOCAL

Bit 11: End Of Calibration flag.

CCRDY

Bit 13: Channel Configuration Ready flag.

IER

ADC interrupt enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CCRDYIE rw		EOCALIE rw		AWD3IE rw	AWD2IE rw	AWD1IE rw			OVRIE rw	EOSIE rw	EOCIE rw	EOSMPIE rw	ADRDYIE rw

Toggle Fields

ADRDYIE

Bit 0: ADC ready interrupt.

EOSMPIE

Bit 1: ADC group regular end of sampling interrupt.

EOCIE

Bit 2: ADC group regular end of unitary conversion interrupt.

EOSIE

Bit 3: ADC group regular end of sequence conversions interrupt.

OVRIE

Bit 4: ADC group regular overrun interrupt.

AWD1IE

Bit 7: ADC analog watchdog 1 interrupt.

AWD2IE

Bit 8: ADC analog watchdog 2 interrupt.

AWD3IE

Bit 9: ADC analog watchdog 3 interrupt.

EOCALIE

Bit 11: End of calibration interrupt enable.

CCRDYIE

Bit 13: Channel Configuration Ready Interrupt enable.

CR

ADC control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL rw			ADVREGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ADSTP rw		ADSTART rw	ADDIS rw	ADEN rw

Toggle Fields

ADEN

Bit 0: ADC enable.

ADDIS

Bit 1: ADC disable.

ADSTART

Bit 2: ADC group regular conversion start.

ADSTP

Bit 4: ADC group regular conversion stop.

ADVREGEN

Bit 28: ADC voltage regulator enable.

ADCAL

Bit 31: ADC calibration.

CFGR1

ADC configuration register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	AWDCH1CH rw							AWD1EN rw	AWD1SGL rw	CHSELRMOD rw					DISCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AUTOFF rw	WAIT rw	CONT rw	OVRMOD rw	EXTEN rw			EXTSEL rw			ALIGN rw	RES rw		SCANDIR rw	DMACFG rw	DMAEN rw

Toggle Fields

DMAEN

Bit 0: ADC DMA transfer enable.

DMACFG

Bit 1: ADC DMA transfer configuration.

SCANDIR

Bit 2: Scan sequence direction.

RES

Bits 3-4: ADC data resolution.

ALIGN

Bit 5: ADC data alignement.

EXTSEL

Bits 6-8: ADC group regular external trigger source.

EXTEN

Bits 10-11: ADC group regular external trigger polarity.

OVRMOD

Bit 12: ADC group regular overrun configuration.

CONT

Bit 13: ADC group regular continuous conversion mode.

WAIT

Bit 14: Wait conversion mode.

AUTOFF

Bit 15: Auto-off mode.

DISCEN

Bit 16: ADC group regular sequencer discontinuous mode.

CHSELRMOD

Bit 21: Mode selection of the ADC_CHSELR register.

AWD1SGL

Bit 22: ADC analog watchdog 1 monitoring a single channel or all channels.

AWD1EN

Bit 23: ADC analog watchdog 1 enable on scope ADC group regular.

AWDCH1CH

Bits 26-30: ADC analog watchdog 1 monitored channel selection.

CFGR2

ADC configuration register 2

Offset: 0x10, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKMODE rw		LFTRIG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TOVS rw	OVSS rw				OVSR rw				OVSE rw

Toggle Fields

OVSE

Bit 0: ADC oversampler enable on scope ADC group regular.

OVSR

Bits 2-4: ADC oversampling ratio.

OVSS

Bits 5-8: ADC oversampling shift.

TOVS

Bit 9: ADC oversampling discontinuous mode (triggered mode) for ADC group regular.

LFTRIG

Bit 29: Low frequency trigger mode enable.

CKMODE

Bits 30-31: ADC clock mode.

SMPR

ADC sampling time register

Offset: 0x14, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					SMPSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMPSEL rw									SMP2 rw				SMP1 rw

Toggle Fields

SMP1

Bits 0-2: Sampling time selection.

SMP2

Bits 4-6: Sampling time selection.

SMPSEL

Bits 8-26: Channel sampling time selection.

AWD1TR

watchdog threshold register

Offset: 0x20, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT1 rw

Toggle Fields

LT1

Bits 0-11: ADC analog watchdog 1 threshold low.

HT1

Bits 16-27: ADC analog watchdog 1 threshold high.

AWD2TR

watchdog threshold register

Offset: 0x24, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT2 rw

Toggle Fields

LT2

Bits 0-11: ADC analog watchdog 2 threshold low.

HT2

Bits 16-27: ADC analog watchdog 2 threshold high.

CHSELR

channel selection register

Offset: 0x28, reset: 0x0FFF0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													CHSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CHSEL rw

Toggle Fields

CHSEL

Bits 0-18: Channel-x selection.

CHSELR_1

channel selection register CHSELRMOD = 1 in ADC_CFGR1

Offset: 0x28, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SQ8 rw				SQ7 rw				SQ6 rw				SQ5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ4 rw				SQ3 rw				SQ2 rw				SQ1 rw

Toggle Fields

SQ1

Bits 0-3: conversion of the sequence.

SQ2

Bits 4-7: conversion of the sequence.

SQ3

Bits 8-11: conversion of the sequence.

SQ4

Bits 12-15: conversion of the sequence.

SQ5

Bits 16-19: conversion of the sequence.

SQ6

Bits 20-23: conversion of the sequence.

SQ7

Bits 24-27: conversion of the sequence.

SQ8

Bits 28-31: conversion of the sequence.

AWD3TR

watchdog threshold register

Offset: 0x2C, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT3 rw

Toggle Fields

LT3

Bits 0-11: ADC analog watchdog 3 threshold high.

HT3

Bits 16-27: ADC analog watchdog 3 threshold high.

DR

ADC group regular conversion data register

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
regularDATA r

Toggle Fields

regularDATA

Bits 0-15: ADC group regular conversion data.

AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													AWD2CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH rw

Toggle Fields

AWD2CH

Bits 0-18: ADC analog watchdog 2 monitored channel selection.

AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													AWD3CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH rw

Toggle Fields

AWD3CH

Bits 0-18: ADC analog watchdog 3 monitored channel selection.

CALFACT

ADC calibration factors register

Offset: 0xB4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CALFACT rw

Toggle Fields

CALFACT

Bits 0-6: ADC calibration factor in single-ended mode.

CCR

ADC common control register

Offset: 0x308, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							VBATEN rw	TSEN rw	VREFEN rw	PRESC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields

PRESC

Bits 18-21: ADC prescaler.

VREFEN

Bit 22: VREFINT enable.

TSEN

Bit 23: Temperature sensor enable.

VBATEN

Bit 24: VBAT enable.

HWCFGR6

Hardware Configuration Register

Offset: 0x3D8, reset: 0x1F1F1F1F, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			CHMAP23 rw								CHMAP22 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CHMAP21 rw								CHMAP20 rw

Toggle Fields

CHMAP20

Bits 0-4: Input channel mapping.

CHMAP21

Bits 8-12: Input channel mapping.

CHMAP22

Bits 16-20: Input channel mapping.

CHMAP23

Bits 24-28: Input channel mapping.

HWCFGR5

Hardware Configuration Register

Offset: 0x3DC, reset: 0x1F080807, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			CHMAP16 rw								CHMAP17 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CHMAP18 rw								CHMAP19 rw

Toggle Fields

CHMAP19

Bits 0-4: Input channel mapping.

CHMAP18

Bits 8-12: Input channel mapping.

CHMAP17

Bits 16-20: Input channel mapping.

CHMAP16

Bits 24-28: Input channel mapping.

HWCFGR4

Hardware Configuration Register

Offset: 0x3E0, reset: 0x070B0A09, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			CHMAP12 rw								CHMAP13 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CHMAP14 rw								CHMAP15 rw

Toggle Fields

CHMAP15

Bits 0-4: Input channel mapping.

CHMAP14

Bits 8-12: Input channel mapping.

CHMAP13

Bits 16-20: Input channel mapping.

CHMAP12

Bits 24-28: Input channel mapping.

HWCFGR3

Hardware Configuration Register

Offset: 0x3E4, reset: 0x07060605, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			CHMAP8 rw								CHMAP9 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CHMAP10 rw								CHMAP11 rw

Toggle Fields

CHMAP11

Bits 0-4: Input channel mapping.

CHMAP10

Bits 8-12: Input channel mapping.

CHMAP9

Bits 16-20: Input channel mapping.

CHMAP8

Bits 24-28: Input channel mapping.

HWCFGR2

Hardware Configuration Register

Offset: 0x3E8, reset: 0x05050404, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			CHMAP4 rw								CHMAP5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CHMAP6 rw								CHMAP7 rw

Toggle Fields

CHMAP7

Bits 0-4: Input channel mapping.

CHMAP6

Bits 8-12: Input channel mapping.

CHMAP5

Bits 16-20: Input channel mapping.

CHMAP4

Bits 24-28: Input channel mapping.

HWCFGR1

Hardware Configuration Register

Offset: 0x3EC, reset: 0x03020100, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			CHMAP0 rw								CHMAP1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CHMAP2 rw								CHMAP3 rw

Toggle Fields

CHMAP3

Bits 0-4: Input channel mapping.

CHMAP2

Bits 8-12: Input channel mapping.

CHMAP1

Bits 16-20: Input channel mapping.

CHMAP0

Bits 24-28: Input channel mapping.

HWCFGR0

Hardware Configuration Register

Offset: 0x3F0, reset: 0x00000110, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OVS r				EXTRA_AWDS r				NUM_CHAN_24 r

Toggle Fields

NUM_CHAN_24

Bits 0-3: NUM_CHAN_24.

EXTRA_AWDS

Bits 4-7: Extra analog watchdog.

OVS

Bits 8-11: Oversampling.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3F8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3FC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size Identification.

COMP

0x40010200: COMP1

0/22 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	COMP1_CSR	LOCK	VALUE						BLANKSEL					PWRMODE		HYST		POLARITY	WINOUT			WINMODE		INPSEL		INMSEL							EN
0x4	COMP2_CSR	LOCK	VALUE						BLANKSEL					PWRMODE		HYST		POLARITY	WINOUT			WINMODE		INPSEL		INMSEL							EN

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw	VALUE rw						BLANKSEL rw					PWRMODE rw		HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY rw	WINOUT rw			WINMODE rw		INPSEL rw		INMSEL rw							EN rw

Toggle Fields

EN

Bit 0: COMP channel 1 enable bit.

INMSEL

Bits 4-7: Comparator 2 signal selector for inverting input INM.

INPSEL

Bits 8-9: Comparator 2 signal selector for non-inverting input.

WINMODE

Bit 11: Comparator 2 non-inverting input selector for window mode.

WINOUT

Bit 14: Comparator 2 output selector.

POLARITY

Bit 15: Comparator 2 polarity selector.

HYST

Bits 16-17: Comparator 2 hysteresis selector.

PWRMODE

Bits 18-19: Comparator 2 power mode selector.

BLANKSEL

Bits 20-24: Comparator 2 blanking source selector.

VALUE

Bit 30: Comparator 2 output status.

LOCK

Bit 31: COMP2_CSR register lock.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw	VALUE rw						BLANKSEL rw					PWRMODE rw		HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY rw	WINOUT rw			WINMODE rw		INPSEL rw		INMSEL rw							EN rw

Toggle Fields

EN

Bit 0: COMP channel 1 enable bit.

INMSEL

Bits 4-7: Comparator 2 signal selector for inverting input INM.

INPSEL

Bits 8-9: Comparator 2 signal selector for non-inverting input.

WINMODE

Bit 11: Comparator 2 non-inverting input selector for window mode.

WINOUT

Bit 14: Comparator 2 output selector.

POLARITY

Bit 15: Comparator 2 polarity selector.

HYST

Bits 16-17: Comparator 2 hysteresis selector.

PWRMODE

Bits 18-19: Comparator 2 power mode selector.

BLANKSEL

Bits 20-24: Comparator 2 blanking source selector.

VALUE

Bit 30: Comparator 2 output status.

LOCK

Bit 31: COMP2_CSR register lock.

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	7	6	4	0
0x0	DR	DR	DR
0x4	IDR	IDR	IDR
0x8	CR			REV_OUT	REV_IN	POLYSIZE	RESET
0x10	INIT	CRC_INIT	CRC_INIT
0x14	POL	POL	POL

DR

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle Fields

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR rw

Toggle Fields

IDR

Bits 0-31: General-purpose 32-bit data register bits.

CR

Control register

Offset: 0x8, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET w

Toggle Fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRC_INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRC_INIT rw

Toggle Fields

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

Toggle Fields

POL

Bits 0-31: Programmable polynomial.

DAC

0x40007400: DAC

10/57 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	25	23	21	20	18	17	16	15	14	13	12	11	9	7	5	4	3	2	1	0
0x0	DAC_CR		CEN2	DMAUDRIE2	DMAEN2	MAMP2		WAVE2	TSEL2			TEN2	EN2		CEN1	DMAUDRIE1	DMAEN1	MAMP1		WAVE1	TSEL1				TEN1	EN1
0x4	DAC_SWTRGR																								SWTRIG2	SWTRIG1
0x8	DAC_DHR12R1																	DACC1DHR
0xC	DAC_DHR12L1													DACC1DHR
0x10	DAC_DHR8R1																			DACC1DHR
0x14	DAC_DHR12R2																	DACC2DHR
0x18	DAC_DHR12L2													DACC2DHR
0x1C	DAC_DHR8R2																			DACC2DHR
0x20	DAC_DHR12RD					DACC2DHR												DACC1DHR
0x24	DAC_DHR12LD	DACC2DHR												DACC1DHR
0x28	DAC_DHR8RD													DACC2DHR						DACC1DHR
0x2C	DAC_DOR1																	DACC1DOR
0x30	DAC_DOR2																	DACC2DOR
0x34	DAC_SR	BWST2	CAL_FLAG2	DMAUDR2										BWST1	CAL_FLAG1	DMAUDR1
0x38	DAC_CCR									OTRIM2												OTRIM1
0x3C	DAC_MCR										MODE2													MODE1
0x40	DAC_SHSR1																		TSAMPLE1
0x44	DAC_SHSR2																		TSAMPLE2
0x48	DAC_SHHR						THOLD2												THOLD1
0x4C	DAC_SHRR							TREFRESH2												TREFRESH1
0x3F0	IP_HWCFGR0							OR_CFG						SAMPLE				TRIANGLE		LFSR			DUAL
0x3F4	VERR																			MAJREV			MINREV
0x3F8	IPIDR	IPID												IPID
0x3FC	SIDR	SID												SID

DAC_CR

DAC control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	CEN2 rw	DMAUDRIE2 rw	DMAEN2 rw	MAMP2 rw				WAVE2 rw		TSEL2 rw				TEN2 rw	EN2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CEN1 rw	DMAUDRIE1 rw	DMAEN1 rw	MAMP1 rw				WAVE1 rw		TSEL1 rw				TEN1 rw	EN1 rw

Toggle Fields

EN1

Bit 0: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1..

TEN1

Bit 1: DAC channel1 trigger enable.

TSEL1

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

DMAEN1

Bit 12: DAC channel1 DMA enable This bit is set and cleared by software..

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software..

CEN1

Bit 14: DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

EN2

Bit 16: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2..

TEN2

Bit 17: DAC channel2 trigger enable.

TSEL2

Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)..

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

DMAEN2

Bit 28: DAC channel2 DMA enable This bit is set and cleared by software..

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software..

CEN2

Bit 30: DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

DAC_SWTRGR

DAC software trigger register

Offset: 0x4, reset: 0x00000000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SWTRIG2 w	SWTRIG1 w

Toggle Fields

SWTRIG1

Bit 0: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register..

SWTRIG2

Bit 1: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register..

DAC_DHR12R1

DAC channel1 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DHR rw

Toggle Fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DAC_DHR12L1

DAC channel1 12-bit left aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR rw

Toggle Fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DAC_DHR8R1

DAC channel1 8-bit right aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DACC1DHR rw

Toggle Fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DAC_DHR12R2

DAC channel2 12-bit right aligned data holding register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC2DHR rw

Toggle Fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DAC_DHR12L2

DAC channel2 12-bit left aligned data holding register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHR rw

Toggle Fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2..

DAC_DHR8R2

DAC channel2 8-bit right-aligned data holding register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DACC2DHR rw

Toggle Fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DAC_DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC2DHR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DHR rw

Toggle Fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DAC_DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DACC2DHR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR rw

Toggle Fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DAC_DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHR rw								DACC1DHR rw

Toggle Fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DAC_DOR1

DAC channel1 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DOR r

Toggle Fields

DACC1DOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

DAC_DOR2

DAC channel2 data output register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC2DOR r

Toggle Fields

DACC2DOR

Bits 0-11: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2..

DAC_SR

DAC status register

Offset: 0x34, reset: 0x00000000, access: Unspecified

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BWST2 r	CAL_FLAG2 r	DMAUDR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BWST1 r	CAL_FLAG1 r	DMAUDR1 rw

Toggle Fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

CAL_FLAG1

Bit 14: DAC Channel 1 calibration offset status This bit is set and cleared by hardware.

BWST1

Bit 15: DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization)..

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

CAL_FLAG2

Bit 30: DAC Channel 2 calibration offset status This bit is set and cleared by hardware.

BWST2

Bit 31: DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization)..

DAC_CCR

DAC calibration control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											OTRIM2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											OTRIM1 rw

Toggle Fields

OTRIM1

Bits 0-4: DAC Channel 1 offset trimming value.

OTRIM2

Bits 16-20: DAC Channel 2 offset trimming value.

DAC_MCR

DAC mode control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													MODE2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													MODE1 rw

Toggle Fields

MODE1

Bits 0-2: DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode.

MODE2

Bits 16-18: DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode.

DAC_SHSR1

DAC Sample and Hold sample time register 1

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TSAMPLE1 rw

Toggle Fields

TSAMPLE1

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

DAC_SHSR2

DAC Sample and Hold sample time register 2

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TSAMPLE2 rw

Toggle Fields

TSAMPLE2

Bits 0-9: DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored..

DAC_SHHR

DAC Sample and Hold hold time register

Offset: 0x48, reset: 0x00010001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						THOLD2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						THOLD1 rw

Toggle Fields

THOLD1

Bits 0-9: DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI.

THOLD2

Bits 16-25: DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI.

DAC_SHRR

DAC Sample and Hold refresh time register

Offset: 0x4C, reset: 0x00010001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TREFRESH2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TREFRESH1 rw

Toggle Fields

TREFRESH1

Bits 0-7: DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI.

TREFRESH2

Bits 16-23: DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI.

IP_HWCFGR0

DAC IP Hardware Configuration Register

Offset: 0x3F0, reset: 0x00001111, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								OR_CFG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SAMPLE rw				TRIANGLE rw				LFSR rw				DUAL rw

Toggle Fields

DUAL

Bits 0-3: Dual DAC capability.

LFSR

Bits 4-7: Pseudonoise wave generation capability.

TRIANGLE

Bits 8-11: Triangle wave generation capability.

SAMPLE

Bits 12-15: Sample and hold mode capability.

OR_CFG

Bits 16-23: option register bit width.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0x00000031, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3F8, reset: 0x00110011, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size Identification.

DBG

0x40015800: Debug support

2/19 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	21	18	17	16	15	12	11	10	5	4	2	1	0
0x0	IDCODE	REV_ID						DEV_ID
0x4	CR													DBG_STANDBY	DBG_STOP
0x8	APB_FZ1	DBG_LPTIM1_STOP	DBG_LPTIM2_STOP	DBG_I2C1_STOP					DBG_IWDG_STOP	DBG_WWDG_STOP	DBG_RTC_STOP	DBG_TIM7_STOP	DBG_TIMER6_STOP		DBG_TIM3_STOP	DBG_TIMER2_STOP
0xC	APB_FZ2				DBG_TIM17_STOP	DBG_TIM16_STOP	DBG_TIM15_STOP	DBG_TIM14_STOP		DBG_TIM1_STOP

IDCODE

MCU Device ID Code Register

Offset: 0x0, reset: 0x0, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REV_ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEV_ID r

Toggle Fields

DEV_ID

Bits 0-15: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

CR

Debug MCU Configuration Register

Offset: 0x4, reset: 0x0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													DBG_STANDBY rw	DBG_STOP rw

Toggle Fields

DBG_STOP

Bit 1: Debug Stop Mode.

DBG_STANDBY

Bit 2: Debug Standby Mode.

APB_FZ1

DBG APB freeze register 1

Offset: 0x8, reset: 0x0, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DBG_LPTIM1_STOP rw	DBG_LPTIM2_STOP rw									DBG_I2C1_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBG_IWDG_STOP rw	DBG_WWDG_STOP rw	DBG_RTC_STOP rw					DBG_TIM7_STOP rw	DBG_TIMER6_STOP rw			DBG_TIM3_STOP rw	DBG_TIMER2_STOP rw

Toggle Fields

DBG_TIMER2_STOP

Bit 0: Debug Timer 2 stopped when Core is halted.

DBG_TIM3_STOP

Bit 1: TIM3 counter stopped when core is halted.

DBG_TIMER6_STOP

Bit 4: Debug Timer 6 stopped when Core is halted.

DBG_TIM7_STOP

Bit 5: TIM7 counter stopped when core is halted.

DBG_RTC_STOP

Bit 10: Debug RTC stopped when Core is halted.

DBG_WWDG_STOP

Bit 11: Debug Window Wachdog stopped when Core is halted.

DBG_IWDG_STOP

Bit 12: Debug Independent Wachdog stopped when Core is halted.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout mode stopped when core is halted.

DBG_LPTIM2_STOP

Bit 30: Clocking of LPTIMER2 counter when the core is halted.

DBG_LPTIM1_STOP

Bit 31: Clocking of LPTIMER1 counter when the core is halted.

APB_FZ2

DBG APB freeze register 2

Offset: 0xC, reset: 0x0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_TIM17_STOP rw	DBG_TIM16_STOP rw	DBG_TIM15_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBG_TIM14_STOP rw				DBG_TIM1_STOP rw

Toggle Fields

DBG_TIM1_STOP

Bit 11: DBG_TIM1_STOP.

DBG_TIM14_STOP

Bit 15: DBG_TIM14_STOP.

DBG_TIM15_STOP

Bit 16: DBG_TIM15_STOP.

DBG_TIM16_STOP

Bit 17: DBG_TIM16_STOP.

DBG_TIM17_STOP

Bit 18: DBG_TIM17_STOP.

DMA

0x40020000: DMA controller

28/71 fields covered. Toggle Registers

Show register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x0	ISR		TEIF7	HTIF7	TCIF7	GIF7	TEIF6	HTIF6	TCIF6	GIF6	TEIF5	HTIF5	TCIF5	GIF5	TEIF4	HTIF4	TCIF4	GIF4	TEIF3	HTIF3	TCIF3	GIF3	TEIF2	HTIF2	TCIF2	GIF2	TEIF1	HTIF1	TCIF1	GIF1
0x4	IFCR		CTEIF27	CHTIF26	CTCIF25	CGIF24	CTEIF23	CHTIF22	CTCIF21	CGIF20	CTEIF19	CHTIF18	CTCIF17	CGIF16	CTEIF4	CHTIF14	CTCIF13	CGIF12	CTEIF11	CHTIF10	CTCIF9	CGIF8	CTEIF7	CHTIF6	CTCIF5	CGIF4	CTEIF3	CHTIF2	CTCIF1	CGIF1
0x4	NDTR														NDT
0x8	PAR	PA													PA
0xC	MAR	MA													MA

CR

DMA channel x configuration register

Offset: 0x0, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

ISR

low interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TEIF7 r	HTIF7 r	TCIF7 r	GIF7 r	TEIF6 r	HTIF6 r	TCIF6 r	GIF6 r	TEIF5 r	HTIF5 r	TCIF5 r	GIF5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF4 r	HTIF4 r	TCIF4 r	GIF4 r	TEIF3 r	HTIF3 r	TCIF3 r	GIF3 r	TEIF2 r	HTIF2 r	TCIF2 r	GIF2 r	TEIF1 r	HTIF1 r	TCIF1 r	GIF1 r

Toggle Fields

GIF1

Bit 0: Channel 1 global interrupt flag.

TCIF1

Bit 1: Channel 1 transfer complete flag.

HTIF1

Bit 2: Channel 1 half transfer flag.

TEIF1

Bit 3: Channel 1 transfer error flag.

GIF2

Bit 4: Channel 2 global interrupt flag.

TCIF2

Bit 5: Channel 2 transfer complete flag.

HTIF2

Bit 6: Channel 2 half transfer flag.

TEIF2

Bit 7: Channel 2 transfer error flag.

GIF3

Bit 8: Channel 3 global interrupt flag.

TCIF3

Bit 9: Channel 3 transfer complete flag.

HTIF3

Bit 10: Channel 3 half transfer flag.

TEIF3

Bit 11: Channel 3 transfer error flag.

GIF4

Bit 12: Channel 4 global interrupt flag.

TCIF4

Bit 13: Channel 4 transfer complete flag.

HTIF4

Bit 14: Channel 4 half transfer flag.

TEIF4

Bit 15: Channel 4 transfer error flag.

GIF5

Bit 16: Channel 5 global interrupt flag.

TCIF5

Bit 17: Channel 5 transfer complete flag.

HTIF5

Bit 18: Channel 5 half transfer flag.

TEIF5

Bit 19: Channel 5 transfer error flag.

GIF6

Bit 20: Channel 6 global interrupt flag.

TCIF6

Bit 21: Channel 6 transfer complete flag.

HTIF6

Bit 22: Channel 6 half transfer flag.

TEIF6

Bit 23: Channel 6 transfer error flag.

GIF7

Bit 24: Channel 7 global interrupt flag.

TCIF7

Bit 25: Channel 7 transfer complete flag.

HTIF7

Bit 26: Channel 7 half transfer flag.

TEIF7

Bit 27: Channel 7 transfer error flag.

IFCR

high interrupt status register

Offset: 0x4, reset: 0x00000000, access: write-only

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTEIF27 w	CHTIF26 w	CTCIF25 w	CGIF24 w	CTEIF23 w	CHTIF22 w	CTCIF21 w	CGIF20 w	CTEIF19 w	CHTIF18 w	CTCIF17 w	CGIF16 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF4 w	CHTIF14 w	CTCIF13 w	CGIF12 w	CTEIF11 w	CHTIF10 w	CTCIF9 w	CGIF8 w	CTEIF7 w	CHTIF6 w	CTCIF5 w	CGIF4 w	CTEIF3 w	CHTIF2 w	CTCIF1 w	CGIF1 w

Toggle Fields

CGIF1

Bit 0: Clear channel 1 global interrupt flag.

CTCIF1

Bit 1: Clear channel 1 transfer complete flag.

CHTIF2

Bit 2: Clear channel 2 half transfer flag.

CTEIF3

Bit 3: Clear channel 3 transfer error flag.

CGIF4

Bit 4: Clear channel 4 global interrupt flag.

CTCIF5

Bit 5: Clear channel 5 transfer complete flag.

CHTIF6

Bit 6: Clear channel 6 half transfer flag.

CTEIF7

Bit 7: Clear channel 7 transfer error flag.

CGIF8

Bit 8: Channel global interrupt flag.

CTCIF9

Bit 9: Channel transfer complete flag.

CHTIF10

Bit 10: Channel half transfer flag.

CTEIF11

Bit 11: Channel transfer error flag.

CGIF12

Bit 12: Channel global interrupt flag.

CTCIF13

Bit 13: Channel transfer complete flag.

CHTIF14

Bit 14: Channel half transfer flag.

CTEIF4

Bit 15: Clear channel 4 transfer error flag.

CGIF16

Bit 16: Channel global interrupt flag.

CTCIF17

Bit 17: Channel transfer complete flag.

CHTIF18

Bit 18: Channel half transfer flag.

CTEIF19

Bit 19: Channel transfer error flag.

CGIF20

Bit 20: Channel global interrupt flag.

CTCIF21

Bit 21: Channel transfer complete flag.

CHTIF22

Bit 22: Channel half transfer flag.

CTEIF23

Bit 23: Channel transfer error flag.

CGIF24

Bit 24: Channel global interrupt flag.

CTCIF25

Bit 25: Channel transfer complete flag.

CHTIF26

Bit 26: Channel half transfer flag.

CTEIF27

Bit 27: Channel transfer error flag.

NDTR

DMA channel x number of data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields

NDT

Bits 0-15: Number of data to transfer.

PAR

DMA channel x peripheral address register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields

PA

Bits 0-31: Peripheral address.

MAR

DMA channel x memory address register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields

MA

Bits 0-31: Memory address.

DMAMUX

0x40020800: DMAMUX

11/82 fields covered. Toggle Registers

Show register map

Offset	Name	31	28	23	18	16	15	9	8	7	6	4	3
0x0	DMAMUX_C0CR		SYNC_ID	NBREQ	SPOL	SE		EGE	SOIE	DMAREQ_ID
0x4	DMAMUX_C1CR		SYNC_ID	NBREQ	SPOL	SE		EGE	SOIE	DMAREQ_ID
0x8	DMAMUX_C2CR		SYNC_ID	NBREQ	SPOL	SE		EGE	SOIE	DMAREQ_ID
0xC	DMAMUX_C3CR		SYNC_ID	NBREQ	SPOL	SE		EGE	SOIE	DMAREQ_ID
0x10	DMAMUX_C4CR		SYNC_ID	NBREQ	SPOL	SE		EGE	SOIE	DMAREQ_ID
0x14	DMAMUX_C5CR		SYNC_ID	NBREQ	SPOL	SE		EGE	SOIE	DMAREQ_ID
0x18	DMAMUX_C6CR		SYNC_ID	NBREQ	SPOL	SE		EGE	SOIE	DMAREQ_ID
0x80	DMAMUX_CSR										SOF
0x84	DMAMUX_CFR										CSOF
0x100	DMAMUX_RG0CR			GNBREQ	GPOL	GE			OIE			SIG_ID
0x104	DMAMUX_RG1CR			GNBREQ	GPOL	GE			OIE			SIG_ID
0x108	DMAMUX_RG2CR			GNBREQ	GPOL	GE			OIE			SIG_ID
0x10C	DMAMUX_RG3CR			GNBREQ	GPOL	GE			OIE			SIG_ID
0x140	DMAMUX_RGSR												OF
0x144	DMAMUX_RGCFR												COF
0x3EC	DMAMUX_HWCFGR2									NUM_DMA_EXT_REQ
0x3F0	DMAMUX_HWCFGR1	NUM_DMA_REQGEN		NUM_DMA_TRIG			NUM_DMA_PERIPH_REQ			NUM_DMA_STREAMS
0x3F4	DMAMUX_VERR									MAJREV			MINREV
0x3F8	DMAMUX_IPIDR	ID					ID
0x3FC	DMAMUX_SIDR	SID					SID

DMAMUX_C0CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

EGE

Bit 9: Event generation enable/disable.

SE

Bit 16: Synchronous operating mode enable/disable.

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

SYNC_ID

Bits 24-28: Synchronization input selected.

DMAMUX_C1CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

EGE

Bit 9: Event generation enable/disable.

SE

Bit 16: Synchronous operating mode enable/disable.

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

NBREQ

SYNC_ID

Bits 24-28: Synchronization input selected.

DMAMUX_C2CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

EGE

Bit 9: Event generation enable/disable.

SE

Bit 16: Synchronous operating mode enable/disable.

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

NBREQ

SYNC_ID

Bits 24-28: Synchronization input selected.

DMAMUX_C3CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

EGE

Bit 9: Event generation enable/disable.

SE

Bit 16: Synchronous operating mode enable/disable.

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

NBREQ

SYNC_ID

Bits 24-28: Synchronization input selected.

DMAMUX_C4CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

EGE

Bit 9: Event generation enable/disable.

SE

Bit 16: Synchronous operating mode enable/disable.

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

NBREQ

SYNC_ID

Bits 24-28: Synchronization input selected.

DMAMUX_C5CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

EGE

Bit 9: Event generation enable/disable.

SE

Bit 16: Synchronous operating mode enable/disable.

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

NBREQ

SYNC_ID

Bits 24-28: Synchronization input selected.

DMAMUX_C6CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

EGE

Bit 9: Event generation enable/disable.

SE

Bit 16: Synchronous operating mode enable/disable.

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

NBREQ

SYNC_ID

Bits 24-28: Synchronization input selected.

DMAMUX_CSR

DMAMUX request line multiplexer interrupt channel status register

Offset: 0x80, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SOF r

Toggle Fields

SOF

Bits 0-6: Synchronization overrun event flag.

DMAMUX_CFR

DMAMUX request line multiplexer interrupt clear flag register

Offset: 0x84, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CSOF w

Toggle Fields

CSOF

Bits 0-6: Clear synchronization overrun event flag.

DMAMUX_RG0CR

DMAMux - DMA request generator channel x control register

Offset: 0x100, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle Fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

OIE

Bit 8: Interrupt enable at trigger event overrun.

GE

Bit 16: DMA request generator channel enable/disable.

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

DMAMUX_RG1CR

DMAMux - DMA request generator channel x control register

Offset: 0x104, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle Fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

OIE

Bit 8: Interrupt enable at trigger event overrun.

GE

Bit 16: DMA request generator channel enable/disable.

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

GNBREQ

DMAMUX_RG2CR

DMAMux - DMA request generator channel x control register

Offset: 0x108, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle Fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

OIE

Bit 8: Interrupt enable at trigger event overrun.

GE

Bit 16: DMA request generator channel enable/disable.

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

GNBREQ

DMAMUX_RG3CR

DMAMux - DMA request generator channel x control register

Offset: 0x10C, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle Fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

OIE

Bit 8: Interrupt enable at trigger event overrun.

GE

Bit 16: DMA request generator channel enable/disable.

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

GNBREQ

DMAMUX_RGSR

DMAMux - DMA request generator status register

Offset: 0x140, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												OF r

Toggle Fields

OF

Bits 0-3: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

DMAMUX_RGCFR

DMAMux - DMA request generator clear flag register

Offset: 0x144, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												COF w

Toggle Fields

COF

Bits 0-3: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

DMAMUX_HWCFGR2

DMAMUX hardware configuration 2 register

Offset: 0x3EC, reset: 0x00000017, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								NUM_DMA_EXT_REQ r

Toggle Fields

NUM_DMA_EXT_REQ

Bits 0-7: Number of DMA request trigger inputs.

DMAMUX_HWCFGR1

DMAMUX hardware configuration 1 register

Offset: 0x3F0, reset: 0x04173907, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NUM_DMA_REQGEN r								NUM_DMA_TRIG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NUM_DMA_PERIPH_REQ r								NUM_DMA_STREAMS r

Toggle Fields

NUM_DMA_STREAMS

Bits 0-7: number of DMA request line multiplexer (output) channels.

NUM_DMA_PERIPH_REQ

Bits 8-15: number of DMA request lines from peripherals.

NUM_DMA_TRIG

Bits 16-23: number of synchronization inputs.

NUM_DMA_REQGEN

Bits 24-31: number of DMA request generator channels.

DMAMUX_VERR

DMAMUX version register

Offset: 0x3F4, reset: 0x00000011, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor IP revision.

MAJREV

Bits 4-7: Major IP revision.

DMAMUX_IPIDR

DMAMUX IP identification register

Offset: 0x3F8, reset: 0x00100011, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle Fields

ID

Bits 0-31: IP identification.

DMAMUX_SIDR

DMAMUX size identification register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size identification.

EXTI

0x40021800: External interrupt/event controller

180/186 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	RTSR1														TR18	TR17	TR16	TR15	TR14	TR13	TR12	TR11	TR10	TR9	TR8	TR7	TR6	TR5	TR4	TR3	TR2	TR1	TR0
0x4	FTSR1														TR18	TR17	TR16	TR15	TR14	TR13	TR12	TR11	TR10	TR9	TR8	TR7	TR6	TR5	TR4	TR3	TR2	TR1	TR0
0x8	SWIER1														SWIER18	SWIER17	SWIER16	SWIER15	SWIER14	SWIER13	SWIER12	SWIER11	SWIER10	SWIER9	SWIER8	SWIER7	SWIER6	SWIER5	SWIER4	SWIER3	SWIER2	SWIER1	SWIER0
0xC	RPR1														RPIF18	RPIF17	RPIF16	RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
0x10	FPR1														FPIF18	FPIF17	FPIF16	FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
0x60	EXTICR1	EXTI24_31								EXTI16_23								EXTI8_15								EXTI0_7
0x64	EXTICR2	EXTI24_31								EXTI16_23								EXTI8_15								EXTI0_7
0x68	EXTICR3	EXTI24_31								EXTI16_23								EXTI8_15								EXTI0_7
0x6C	EXTICR4	EXTI24_31								EXTI16_23								EXTI8_15								EXTI0_7
0x80	IMR1	IM31	IM30	IM29	IM28	IM27	IM26	IM25	IM24	IM23	IM22	IM21	IM20	IM19	IM18	IM17	IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0x84	EMR1	EM31	EM30	EM29	EM28	EM27	EM26	EM25		EM23		EM21		EM19	EM18	EM17	EM16	EM15	EM14	EM13	EM12	EM11	EM10	EM9	EM8	EM7	EM6	EM5	EM4	EM3	EM2	EM1	EM0
0x90	IMR2																															IM33	IM32
0x94	EMR2																															EM33	EM32
0x3D8	HWCFGR7	CPUEVENT																CPUEVENT
0x3DC	HWCFGR6	CPUEVENT																CPUEVENT
0x3E0	HWCFGR5	CPUEVENT																CPUEVENT
0x3E4	HWCFGR4	EVENT_TRG																EVENT_TRG
0x3E8	HWCFGR3	EVENT_TRG																EVENT_TRG
0x3EC	HWCFGR2	EVENT_TRG																EVENT_TRG
0x3F0	HWCFGR1									NBIOPORT								CPUEVTEN				NBCPUS				NBEVENTS

RTSR1

EXTI rising trigger selection register

Offset: 0x0, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													TR18 rw	TR17 rw	TR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TR15 rw	TR14 rw	TR13 rw	TR12 rw	TR11 rw	TR10 rw	TR9 rw	TR8 rw	TR7 rw	TR6 rw	TR5 rw	TR4 rw	TR3 rw	TR2 rw	TR1 rw	TR0 rw

Toggle Fields

TR0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR1

EXTI falling trigger selection register

Offset: 0x4, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													TR18 rw	TR17 rw	TR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TR15 rw	TR14 rw	TR13 rw	TR12 rw	TR11 rw	TR10 rw	TR9 rw	TR8 rw	TR7 rw	TR6 rw	TR5 rw	TR4 rw	TR3 rw	TR2 rw	TR1 rw	TR0 rw

Toggle Fields

TR0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER1

EXTI software interrupt event register

Offset: 0x8, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SWIER18 rw	SWIER17 rw	SWIER16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWIER15 rw	SWIER14 rw	SWIER13 rw	SWIER12 rw	SWIER11 rw	SWIER10 rw	SWIER9 rw	SWIER8 rw	SWIER7 rw	SWIER6 rw	SWIER5 rw	SWIER4 rw	SWIER3 rw	SWIER2 rw	SWIER1 rw	SWIER0 rw

Toggle Fields

SWIER0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER17

Bit 17: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

RPR1

EXTI rising edge pending register

Offset: 0xC, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													RPIF18 rw	RPIF17 rw	RPIF16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RPIF15 rw	RPIF14 rw	RPIF13 rw	RPIF12 rw	RPIF11 rw	RPIF10 rw	RPIF9 rw	RPIF8 rw	RPIF7 rw	RPIF6 rw	RPIF5 rw	RPIF4 rw	RPIF3 rw	RPIF2 rw	RPIF1 rw	RPIF0 rw

Toggle Fields

RPIF0

Bit 0: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF1

Bit 1: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF2

Bit 2: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF3

Bit 3: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF4

Bit 4: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF5

Bit 5: configurable event inputs x rising edge Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF6

Bit 6: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF7

Bit 7: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF8

Bit 8: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF9

Bit 9: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF10

Bit 10: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF11

Bit 11: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF12

Bit 12: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF13

Bit 13: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF14

Bit 14: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF15

Bit 15: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF16

Bit 16: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF17

Bit 17: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RPIF18

Bit 18: configurable event inputs x rising edge Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPR1

EXTI falling edge pending register

Offset: 0x10, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FPIF18 rw	FPIF17 rw	FPIF16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FPIF15 rw	FPIF14 rw	FPIF13 rw	FPIF12 rw	FPIF11 rw	FPIF10 rw	FPIF9 rw	FPIF8 rw	FPIF7 rw	FPIF6 rw	FPIF5 rw	FPIF4 rw	FPIF3 rw	FPIF2 rw	FPIF1 rw	FPIF0 rw

Toggle Fields

FPIF0

Bit 0: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF1

Bit 1: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF2

Bit 2: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF3

Bit 3: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF4

Bit 4: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF5

Bit 5: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF6

Bit 6: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF7

Bit 7: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF8

Bit 8: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF9

Bit 9: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF10

Bit 10: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF11

Bit 11: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF12

Bit 12: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF13

Bit 13: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF14

Bit 14: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF15

Bit 15: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF16

Bit 16: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF17

Bit 17: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FPIF18

Bit 18: configurable event inputs x falling edge pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

EXTICR1

EXTI external interrupt selection register

Offset: 0x60, reset: 0x00000000, access: read-write

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI24_31 rw								EXTI16_23 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI8_15 rw								EXTI0_7 rw

Toggle Fields

EXTI0_7

Bits 0-7: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI8_15

Bits 8-15: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI16_23

Bits 16-23: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI24_31

Bits 24-31: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTICR2

EXTI external interrupt selection register

Offset: 0x64, reset: 0x00000000, access: read-write

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI24_31 rw								EXTI16_23 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI8_15 rw								EXTI0_7 rw

Toggle Fields

EXTI0_7

Bits 0-7: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI8_15

Bits 8-15: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI16_23

Bits 16-23: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI24_31

Bits 24-31: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTICR3

EXTI external interrupt selection register

Offset: 0x68, reset: 0x00000000, access: read-write

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI24_31 rw								EXTI16_23 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI8_15 rw								EXTI0_7 rw

Toggle Fields

EXTI0_7

Bits 0-7: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI8_15

Bits 8-15: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI16_23

Bits 16-23: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI24_31

Bits 24-31: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTICR4

EXTI external interrupt selection register

Offset: 0x6C, reset: 0x00000000, access: read-write

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI24_31 rw								EXTI16_23 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI8_15 rw								EXTI0_7 rw

Toggle Fields

EXTI0_7

Bits 0-7: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI8_15

Bits 8-15: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI16_23

Bits 16-23: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

EXTI24_31

Bits 24-31: GPIO port selection.

Allowed values:
0: PA: GPIO port A selected
1: PB: GPIO port B selected
2: PC: GPIO port C selected
3: PD: GPIO port D selected
5: PF: GPIO port F selected

IMR1

EXTI CPU wakeup with interrupt mask register

Offset: 0x80, reset: 0xFFF80000, access: read-write

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IM31 rw	IM30 rw	IM29 rw	IM28 rw	IM27 rw	IM26 rw	IM25 rw	IM24 rw	IM23 rw	IM22 rw	IM21 rw	IM20 rw	IM19 rw	IM18 rw	IM17 rw	IM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15 rw	IM14 rw	IM13 rw	IM12 rw	IM11 rw	IM10 rw	IM9 rw	IM8 rw	IM7 rw	IM6 rw	IM5 rw	IM4 rw	IM3 rw	IM2 rw	IM1 rw	IM0 rw

Toggle Fields

IM0

Bit 0: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM1

Bit 1: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM2

Bit 2: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM3

Bit 3: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM4

Bit 4: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM5

Bit 5: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM6

Bit 6: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM7

Bit 7: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM8

Bit 8: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM9

Bit 9: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM10

Bit 10: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM11

Bit 11: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM12

Bit 12: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM13

Bit 13: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM14

Bit 14: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM15

Bit 15: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM16

Bit 16: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM17

Bit 17: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM18

Bit 18: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM19

Bit 19: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM20

Bit 20: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM21

Bit 21: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM22

Bit 22: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM23

Bit 23: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM24

Bit 24: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM25

Bit 25: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM26

Bit 26: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM27

Bit 27: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM28

Bit 28: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM29

Bit 29: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM30

Bit 30: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM31

Bit 31: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR1

EXTI CPU wakeup with event mask register

Offset: 0x84, reset: 0x00000000, access: read-write

29/29 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EM31 rw	EM30 rw	EM29 rw	EM28 rw	EM27 rw	EM26 rw	EM25 rw		EM23 rw		EM21 rw		EM19 rw	EM18 rw	EM17 rw	EM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM15 rw	EM14 rw	EM13 rw	EM12 rw	EM11 rw	EM10 rw	EM9 rw	EM8 rw	EM7 rw	EM6 rw	EM5 rw	EM4 rw	EM3 rw	EM2 rw	EM1 rw	EM0 rw

Toggle Fields

EM0

Bit 0: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM1

Bit 1: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM2

Bit 2: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM3

Bit 3: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM4

Bit 4: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM5

Bit 5: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM6

Bit 6: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM7

Bit 7: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM8

Bit 8: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM9

Bit 9: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM10

Bit 10: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM11

Bit 11: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM12

Bit 12: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM13

Bit 13: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM14

Bit 14: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM15

Bit 15: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM16

Bit 16: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM17

Bit 17: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM18

Bit 18: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM19

Bit 19: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM21

Bit 21: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM23

Bit 23: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM25

Bit 25: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM26

Bit 26: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM27

Bit 27: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM28

Bit 28: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM29

Bit 29: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM30

Bit 30: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM31

Bit 31: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IMR2

EXTI CPU wakeup with interrupt mask register

Offset: 0x90, reset: 0xFFFFFFFF, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														IM33 rw	IM32 rw

Toggle Fields

IM32

Bit 0: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM33

Bit 1: CPU wakeup with interrupt mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR2

EXTI CPU wakeup with event mask register

Offset: 0x94, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EM33 rw	EM32 rw

Toggle Fields

EM32

Bit 0: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EM33

Bit 1: CPU wakeup with event mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

HWCFGR7

Hardware configuration registers

Offset: 0x3D8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT rw

Toggle Fields

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR6

Hardware configuration registers

Offset: 0x3DC, reset: 0x00000003, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT rw

Toggle Fields

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR5

Hardware configuration registers

Offset: 0x3E0, reset: 0xFEAFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT rw

Toggle Fields

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR4

Hardware configuration registers

Offset: 0x3E4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG rw

Toggle Fields

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR3

Hardware configuration registers

Offset: 0x3E8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG rw

Toggle Fields

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR2

Hardware configuration registers

Offset: 0x3EC, reset: 0x0007FFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG rw

Toggle Fields

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR1

Hardware configuration registers

Offset: 0x3F0, reset: 0x00051021, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								NBIOPORT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVTEN r				NBCPUS r				NBEVENTS r

Toggle Fields

NBEVENTS

Bits 0-7: configuration number of event.

NBCPUS

Bits 8-11: configuration number of CPUs.

CPUEVTEN

Bits 12-15: HW configuration of CPU event output enable.

NBIOPORT

Bits 16-23: HW configuration of number of IO ports.

FLASH

0x40022000: Flash

13/68 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ACR													DBG_SWEN		EMPTY					ICRST		ICEN	PRFTEN						LATENCY
0x8	KEYR	KEYR															KEYR
0xC	OPTKEYR	OPTKEYR															OPTKEYR
0x10	SR													CFGBSY		BSY	OPTVERR	RDERR					FASTERR	MISERR	PGSERR	SIZERR	PGAERR	WRPERR	PROGERR		OPERR	EOP
0x14	CR	LOCK	OPTLOCK		SEC_PROT	OBL_LAUNCH	RDERRIE	ERRIE	EOPIE					FSTPG	OPTSTRT	STRT								PNB						MER	PER	PG
0x18	ECCR	ECCD	ECCC						ECCIE			SYSF_ECC							ADDR_ECC
0x20	OPTR			IRHEN	NRST_MODE		nBOOT0	nBOOT1	nBOOT_SEL	RAM_PARITY_CHECK			WWDG_SW	IWDG_STDBY	IWDG_STOP	IDWG_SW	nRSTS_HDW	nRST_STDBY	nRST_STOP	BORR_LEV		BORF_LEV		BOREN	RDP
0x24	PCROP1ASR																								PCROP1A_STRT
0x28	PCROP1AER	PCROP_RDP																							PCROP1A_END
0x2C	WRP1AR										WRP1A_END																WRP1A_STRT
0x30	WRP1BR										WRP1B_END																WRP1B_STRT
0x34	PCROP1BSR																								PCROP1B_STRT
0x38	PCROP1BER																								PCROP1B_END
0x80	SECR															BOOT_LOCK										SEC_SIZE

ACR

Access control register

Offset: 0x0, reset: 0x00000600, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_SWEN rw		EMPTY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ICRST rw		ICEN rw	PRFTEN rw						LATENCY rw

Toggle Fields

LATENCY

Bits 0-2: Latency.

PRFTEN

Bit 8: Prefetch enable.

ICEN

Bit 9: Instruction cache enable.

ICRST

Bit 11: Instruction cache reset.

EMPTY

Bit 16: Flash User area empty.

DBG_SWEN

Bit 18: Debug access software enable.

KEYR

Flash key register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEYR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEYR w

Toggle Fields

KEYR

Bits 0-31: KEYR.

OPTKEYR

Option byte key register

Offset: 0xC, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OPTKEYR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTKEYR w

Toggle Fields

OPTKEYR

Bits 0-31: Option byte key.

SR

Status register

Offset: 0x10, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													CFGBSY rw		BSY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTVERR rw	RDERR rw					FASTERR rw	MISERR rw	PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

Toggle Fields

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: Write protected error.

PGAERR

Bit 5: Programming alignment error.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

RDERR

Bit 14: PCROP read error.

OPTVERR

Bit 15: Option and Engineering bits loading validity error.

BSY

Bit 16: Busy.

CFGBSY

Bit 18: Programming or erase configuration busy..

CR

Flash control register

Offset: 0x14, reset: 0xC0000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw	OPTLOCK rw		SEC_PROT rw	OBL_LAUNCH rw	RDERRIE rw	ERRIE rw	EOPIE rw						FSTPG rw	OPTSTRT rw	STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PNB rw						MER rw	PER rw	PG rw

Toggle Fields

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER

Bit 2: Mass erase.

PNB

Bits 3-8: Page number.

STRT

Bit 16: Start.

OPTSTRT

Bit 17: Options modification start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: PCROP read error interrupt enable.

OBL_LAUNCH

Bit 27: Force the option byte loading.

SEC_PROT

Bit 28: Securable memory area protection enable.

OPTLOCK

Bit 30: Options Lock.

LOCK

Bit 31: FLASH_CR Lock.

ECCR

Flash ECC register

Offset: 0x18, reset: 0x00000000, access: Unspecified

2/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ECCD rw	ECCC rw						ECCIE rw				SYSF_ECC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADDR_ECC r

Toggle Fields

ADDR_ECC

Bits 0-13: ECC fail address.

SYSF_ECC

Bit 20: ECC fail for Corrected ECC Error or Double ECC Error in info block.

ECCIE

Bit 24: ECC correction interrupt enable.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x20, reset: 0xF0000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IRHEN rw	NRST_MODE rw		nBOOT0 rw	nBOOT1 rw	nBOOT_SEL rw		RAM_PARITY_CHECK rw			WWDG_SW rw	IWDG_STDBY rw	IWDG_STOP rw	IDWG_SW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
nRSTS_HDW rw	nRST_STDBY rw	nRST_STOP rw	BORR_LEV rw		BORF_LEV rw		BOREN rw	RDP rw

Toggle Fields

RDP

Bits 0-7: Read protection level.

BOREN

Bit 8: BOR reset Level.

BORF_LEV

Bits 9-10: These bits contain the VDD supply level threshold that activates the reset.

BORR_LEV

Bits 11-12: These bits contain the VDD supply level threshold that releases the reset..

nRST_STOP

Bit 13: nRST_STOP.

nRST_STDBY

Bit 14: nRST_STDBY.

nRSTS_HDW

Bit 15: nRSTS_HDW.

IDWG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

RAM_PARITY_CHECK

Bit 22: SRAM parity check control.

nBOOT_SEL

Bit 24: nBOOT_SEL.

nBOOT1

Bit 25: Boot configuration.

nBOOT0

Bit 26: nBOOT0 option bit.

NRST_MODE

Bits 27-28: NRST_MODE.

IRHEN

Bit 29: Internal reset holder enable bit.

PCROP1ASR

Flash PCROP zone A Start address register

Offset: 0x24, reset: 0xF0000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PCROP1A_STRT r

Toggle Fields

PCROP1A_STRT

Bits 0-7: PCROP1A area start offset.

PCROP1AER

Flash PCROP zone A End address register

Offset: 0x28, reset: 0xF0000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PCROP_RDP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PCROP1A_END r

Toggle Fields

PCROP1A_END

Bits 0-7: PCROP1A area end offset.

PCROP_RDP

Bit 31: PCROP area preserved when RDP level decreased.

WRP1AR

Flash WRP area A address register

Offset: 0x2C, reset: 0xF0000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										WRP1A_END r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										WRP1A_STRT r

Toggle Fields

WRP1A_STRT

Bits 0-5: WRP area A start offset.

WRP1A_END

Bits 16-21: WRP area A end offset.

WRP1BR

Flash WRP area B address register

Offset: 0x30, reset: 0xF0000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										WRP1B_END r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										WRP1B_STRT r

Toggle Fields

WRP1B_STRT

Bits 0-5: WRP area B start offset.

WRP1B_END

Bits 16-21: WRP area B end offset.

PCROP1BSR

Flash PCROP zone B Start address register

Offset: 0x34, reset: 0xF0000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PCROP1B_STRT r

Toggle Fields

PCROP1B_STRT

Bits 0-7: PCROP1B area start offset.

PCROP1BER

Flash PCROP zone B End address register

Offset: 0x38, reset: 0xF0000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PCROP1B_END r

Toggle Fields

PCROP1B_END

Bits 0-7: PCROP1B area end offset.

SECR

Flash Security register

Offset: 0x80, reset: 0xF0000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															BOOT_LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SEC_SIZE r

Toggle Fields

SEC_SIZE

Bits 0-6: Securable memory area size.

BOOT_LOCK

Bit 16: used to force boot from user area.

GPIOA

0x50000000: General-purpose I/Os

16/177 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xC	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1C	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

MODER

GPIO port mode register

Offset: 0x0, reset: 0xEBFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x0C000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x24000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOB

0x50000400: General-purpose I/Os

16/177 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xC	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1C	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOC

0x50000800: General-purpose I/Os

16/177 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xC	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1C	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOD

0x50000C00: General-purpose I/Os

16/177 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xC	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1C	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOF

0x50001400: General-purpose I/Os

16/177 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xC	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1C	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

HDMI_CEC

0x40007800: HDMI-CEC

1/40 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CEC_CR													TXEOM	TXSOM	CECEN
0x4	CEC_CFGR	LSTN	OAR					SFTOPT	BRDNOGEN	LBPEGEN	BREGEN	BRESTP	RXTOL	SFT
0x8	CEC_TXDR								TXD
0xC	CEC_RXDR								RXD
0x10	CEC_ISR			TXACKE	TXERR	TXUDR	TXEND	TXBR	ARBLST	RXACKE	LBPE	SBPE	BRE	RXOVR	RXEND	RXBR
0x14	CEC_IER			TXACKIE	TXERRIE	TXUDRIE	TXENDIE	TXBRIE	ARBLSTIE	RXACKIE	LBPEIE	SBPEIE	BREIE	RXOVRIE	RXENDIE	RXBRIE

CEC_CR

CEC control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TXEOM rw	TXSOM rw	CECEN rw

Toggle Fields

CECEN

Bit 0: CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission..

TXSOM

Bit 1: Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception.

TXEOM

Bit 2: Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message).

CEC_CFGR

This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.

Offset: 0x4, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LSTN rw	OAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SFTOPT rw	BRDNOGEN rw	LBPEGEN rw	BREGEN rw	BRESTP rw	RXTOL rw	SFT rw

Toggle Fields

SFT

Bits 0-2: Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods.

RXTOL

Bit 3: Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall.

BRESTP

Bit 4: Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software..

BREGEN

Bit 5: Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0.

LBPEGEN

Bit 6: Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0.

BRDNOGEN

Bit 7: Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software..

SFTOPT

Bit 8: SFT Option Bit The SFTOPT bit is set and cleared by software..

OAR

Bits 16-30: Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received..

LSTN

Bit 31: Listen mode LSTN bit is set and cleared by software..

CEC_TXDR

CEC Tx data register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXD w

Toggle Fields

TXD

Bits 0-7: Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1.

CEC_RXDR

CEC Rx Data Register

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXD r

Toggle Fields

RXD

Bits 0-7: Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line..

CEC_ISR

CEC Interrupt and Status Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TXACKE rw	TXERR rw	TXUDR rw	TXEND rw	TXBR rw	ARBLST rw	RXACKE rw	LBPE rw	SBPE rw	BRE rw	RXOVR rw	RXEND rw	RXBR rw

Toggle Fields

RXBR

Bit 0: Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1..

RXEND

Bit 1: End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1..

RXOVR

Bit 2: Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1..

BRE

Bit 3: Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1..

SBPE

Bit 4: Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1..

LBPE

Bit 5: Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1..

RXACKE

Bit 6: Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1..

ARBLST

Bit 7: Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1..

TXBR

Bit 8: Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1..

TXEND

Bit 9: End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1..

TXUDR

Bit 10: Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1.

TXERR

Bit 11: Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1..

TXACKE

Bit 12: Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1..

CEC_IER

CEC interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TXACKIE rw	TXERRIE rw	TXUDRIE rw	TXENDIE rw	TXBRIE rw	ARBLSTIE rw	RXACKIE rw	LBPEIE rw	SBPEIE rw	BREIE rw	RXOVRIE rw	RXENDIE rw	RXBRIE rw

Toggle Fields

RXBRIE

Bit 0: Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software..

RXENDIE

Bit 1: End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software..

RXOVRIE

Bit 2: Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software..

BREIE

Bit 3: Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software..

SBPEIE

Bit 4: Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software..

LBPEIE

Bit 5: Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software..

RXACKIE

Bit 6: Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software..

ARBLSTIE

Bit 7: Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software..

TXBRIE

Bit 8: Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software..

TXENDIE

Bit 9: Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software..

TXUDRIE

Bit 10: Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software..

TXERRIE

Bit 11: Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software..

TXACKIE

Bit 12: Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software..

I2C1

0x40005400: Inter-integrated circuit

17/78 fields covered. Toggle Registers

Show register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2			PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1														OA1EN					OA1MODE	OA1_8_9		OA1_7_1							OA1_0
0xC	OAR2														OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC					SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN	TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR						ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1C	ICR																ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																						PEC
0x24	RXDR																						RXDATA
0x28	TXDR																						TXDATA

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle Fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle Fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1_8_9 rw		OA1_7_1 rw							OA1_0 rw

Toggle Fields

OA1_0

Bit 0: Interface address.

OA1_7_1

Bits 1-7: Interface address.

OA1_8_9

Bits 8-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle Fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle Fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle Fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle Fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle Fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle Fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle Fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle Fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C2

0x40005800: Inter-integrated circuit

17/78 fields covered. Toggle Registers

Show register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2			PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1														OA1EN					OA1MODE	OA1_8_9		OA1_7_1							OA1_0
0xC	OAR2														OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC					SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN	TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR						ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1C	ICR																ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																						PEC
0x24	RXDR																						RXDATA
0x28	TXDR																						TXDATA

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle Fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle Fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1_8_9 rw		OA1_7_1 rw							OA1_0 rw

Toggle Fields

OA1_0

Bit 0: Interface address.

OA1_7_1

Bits 1-7: Interface address.

OA1_8_9

Bits 8-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle Fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle Fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle Fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle Fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle Fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle Fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle Fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle Fields

TXDATA

Bits 0-7: 8-bit transmit data.

IWDG

0x40003000: Independent watchdog

7/13 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	7	3	2	1	0
0x0	KR		KEY
0x4	PR						PR
0x8	RLR			RL
0xC	SR						WVU	RVU	PVU
0x10	WINR			WIN
0x3F0	HWCFGR				PR_DEFAULT	WINDOW
0x3F4	VERR				MAJREV	MINREV
0x3F8	IPIDR	IPID	IPID
0x3FC	SIDR	SID	SID

KR

Key register

Offset: 0x0, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle Fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

Toggle Fields

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle Fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WVU r	RVU r	PVU r

Toggle Fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

Toggle Fields

WIN

Bits 0-11: Watchdog counter window value.

HWCFGR

hardware configuration register

Offset: 0x3F0, reset: 0x00000071, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PR_DEFAULT rw				WINDOW rw

Toggle Fields

WINDOW

Bits 0-3: Support of Window function.

PR_DEFAULT

Bits 4-7: Prescaler default value.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0x00000023, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3F8, reset: 0x00120041, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size Identification.

LPTIM1

0x40007C00: Low power timer

8/44 fields covered. Toggle Registers

Show register map

Offset	Name	24	23	22	21	20	19	18	15	11	7	6	5	4	3	2	1	0
0x0	ISR											DOWN	UP	ARROK	CMPOK	EXTTRIG	ARRM	CMPM
0x4	ICR											DOWNCF	UPCF	ARROKCF	CMPOKCF	EXTTRIGCF	ARRMCF	CMPMCF
0x8	IER											DOWNIE	UPIE	ARROKIE	CMPOKIE	EXTTRIGIE	ARRMIE	CMPMIE
0xC	CFGR	ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN	TRIGSEL	PRESC	TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR													RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CMP								CMP
0x18	ARR								ARR
0x1C	CNT								CNT
0x24	CFGR2												IN2SEL				IN1SEL

ISR

Interrupt and Status Register

Offset: 0x0, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWN r	UP r	ARROK r	CMPOK r	EXTTRIG r	ARRM r	CMPM r

Toggle Fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNCF w	UPCF w	ARROKCF w	CMPOKCF w	EXTTRIGCF w	ARRMCF w	CMPMCF w

Toggle Fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNIE rw	UPIE rw	ARROKIE rw	CMPOKIE rw	EXTTRIGIE rw	ARRMIE rw	CMPMIE rw

Toggle Fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle Fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle Fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMP rw

Toggle Fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle Fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle Fields

IN1SEL

Bits 0-1: LPTIMx Input 1 selection.

IN2SEL

Bits 4-5: LPTIM1 Input 2 selection.

LPTIM2

0x40009400: Low power timer

8/44 fields covered. Toggle Registers

Show register map

Offset	Name	24	23	22	21	20	19	18	15	11	7	6	5	4	3	2	1	0
0x0	ISR											DOWN	UP	ARROK	CMPOK	EXTTRIG	ARRM	CMPM
0x4	ICR											DOWNCF	UPCF	ARROKCF	CMPOKCF	EXTTRIGCF	ARRMCF	CMPMCF
0x8	IER											DOWNIE	UPIE	ARROKIE	CMPOKIE	EXTTRIGIE	ARRMIE	CMPMIE
0xC	CFGR	ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN	TRIGSEL	PRESC	TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR													RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CMP								CMP
0x18	ARR								ARR
0x1C	CNT								CNT
0x24	CFGR2												IN2SEL				IN1SEL

ISR

Interrupt and Status Register

Offset: 0x0, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWN r	UP r	ARROK r	CMPOK r	EXTTRIG r	ARRM r	CMPM r

Toggle Fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNCF w	UPCF w	ARROKCF w	CMPOKCF w	EXTTRIGCF w	ARRMCF w	CMPMCF w

Toggle Fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNIE rw	UPIE rw	ARROKIE rw	CMPOKIE rw	EXTTRIGIE rw	ARRMIE rw	CMPMIE rw

Toggle Fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle Fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle Fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMP rw

Toggle Fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle Fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle Fields

IN1SEL

Bits 0-1: LPTIMx Input 1 selection.

IN2SEL

Bits 4-5: LPTIM1 Input 2 selection.

LPUART

0x40008000: Universal synchronous asynchronous receiver transmitter

26/100 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1			DEAT					DEDT0						CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD4_7				ADD0_3								MSBFIRST	TAINV	TXINV	RXINV	SWAP		STOP									ADDM7
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG				TXFTIE	WUFIE	WUS						DEP	DEM	DDRE	OVRDIS		CTSIE	CTSE	RTSE	DMAT	DMAR			HDSEL			EIE
0xC	BRR													BRR				BRR
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1C	ISR					TXFT	RXFT		RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY						CTS	CTSIF		TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF								CTSCF			TCCF		IDLECF	ORECF	NCF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2C	PRESC																													PRESCALER
0x3EC	HWCFGR2																									CFG2				CFG1
0x3F0	HWCFGR1	CFG8				CFG7				CFG6				CFG5				CFG4				CFG3				CFG2				CFG1
0x3F4	VERR																									MAJREV				MINREV
0x3F8	IPIDR	IPID																IPID
0x3FC	SIDR	SID																SID

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw			DEAT rw					DEDT0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle Fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

DEDT0

Bits 16-20: DEDT0.

DEAT

Bits 21-25: DEAT0.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw								MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw		STOP rw									ADDM7 rw

Toggle Fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

STOP

Bits 12-13: STOP bits.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw				TXFTIE rw	WUFIE rw	WUS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw		CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw			HDSEL rw			EIE rw

Toggle Fields

EIE

Bit 0: Error interrupt enable.

HDSEL

Bit 3: Half-duplex selection.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BRR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle Fields

BRR

Bits 0-19: BRR.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle Fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

21/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r		RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTS r	CTSIF r		TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle Fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTSCF w			TCCF w		IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle Fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TCCF

Bit 6: Transmission complete clear flag.

CTSCF

Bit 9: CTS clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

LPUART Hardware Configuration register 2

Offset: 0x3EC, reset: 0x00000013, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CFG2 rw				CFG1 rw

Toggle Fields

CFG1

Bits 0-3: LUART hardware configuration 1.

CFG2

Bits 4-7: LUART hardware configuration 2.

HWCFGR1

LPUART Hardware Configuration register 1

Offset: 0x3F0, reset: 0x31100000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CFG8 rw				CFG7 rw				CFG6 rw				CFG5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CFG4 rw				CFG3 rw				CFG2 rw				CFG1 rw

Toggle Fields

CFG1

Bits 0-3: LUART hardware configuration 1.

CFG2

Bits 4-7: LUART hardware configuration 2.

CFG3

Bits 8-11: LUART hardware configuration 1.

CFG4

Bits 12-15: LUART hardware configuration 2.

CFG5

Bits 16-19: LUART hardware configuration 2.

CFG6

Bits 20-23: LUART hardware configuration 2.

CFG7

Bits 24-27: LUART hardware configuration 2.

CFG8

Bits 28-31: LUART hardware configuration 2.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0x00000023, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3F8, reset: 0x00130003, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size Identification.

MPU

0xE000ED90: Memory protection unit

3/19 fields covered. Toggle Registers

Show register map

Offset	Name	31	28	26	23	21	18	17	16	15	7	5	4	3	2	1	0
0x0	MPU_TYPER				IREGION					DREGION							SEPARATE
0x4	MPU_CTRL														PRIVDEFENA	HFNMIENA	ENABLE
0x8	MPU_RNR										REGION
0xC	MPU_RBAR	ADDR								ADDR			VALID	REGION
0x10	MPU_RASR		XN	AP		TEX	S	C	B	SRD		SIZE					ENABLE

MPU_TYPER

MPU type register

Offset: 0x0, reset: 0X00000800, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								IREGION r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DREGION r															SEPARATE r

Toggle Fields

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

MPU_CTRL

MPU control register

Offset: 0x4, reset: 0X00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PRIVDEFENA rw	HFNMIENA rw	ENABLE rw

Toggle Fields

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

MPU_RNR

MPU region number register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REGION rw

Toggle Fields

REGION

Bits 0-7: MPU region.

MPU_RBAR

MPU region base address register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR rw											VALID rw	REGION rw

Toggle Fields

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

MPU_RASR

MPU region attribute and size register

Offset: 0x10, reset: 0X00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			XN rw		AP rw					TEX rw			S rw	C rw	B rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRD rw										SIZE rw					ENABLE rw

Toggle Fields

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

0/36 fields covered. Toggle Registers

Show register map

Offset	Name	31	23	15	7
0x0	ISER	SETENA		SETENA
0x80	ICER	CLRENA		CLRENA
0x100	ISPR	SETPEND		SETPEND
0x180	ICPR	CLRPEND		CLRPEND
0x300	IPR0	PRI_3	PRI_2	PRI_1	PRI_0
0x304	IPR1	PRI_7	PRI_6	PRI_5	PRI_4
0x308	IPR2	PRI_11	PRI_10	PRI_9	PRI_8
0x30C	IPR3	PRI_15	PRI_14	PRI_13	PRI_12
0x310	IPR4	PRI_19	PRI_18	PRI_17	PRI_16
0x314	IPR5	PRI_23	PRI_22	PRI_21	PRI_20
0x318	IPR6	PRI_27	PRI_26	PRI_25	PRI_24
0x31C	IPR7	PRI_31	PRI_30	PRI_29	PRI_28

ISER

Interrupt Set Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle Fields

SETENA

Bits 0-31: SETENA.

ICER

Interrupt Clear Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle Fields

CLRENA

Bits 0-31: CLRENA.

ISPR

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle Fields

SETPEND

Bits 0-31: SETPEND.

ICPR

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle Fields

CLRPEND

Bits 0-31: CLRPEND.

IPR0

Interrupt Priority Register 0

Offset: 0x300, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_3 rw								PRI_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_1 rw								PRI_0 rw

Toggle Fields

PRI_0

Bits 0-7: priority for interrupt 0.

PRI_1

Bits 8-15: priority for interrupt 1.

PRI_2

Bits 16-23: priority for interrupt 2.

PRI_3

Bits 24-31: priority for interrupt 3.

IPR1

Interrupt Priority Register 1

Offset: 0x304, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_7 rw								PRI_6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_5 rw								PRI_4 rw

Toggle Fields

PRI_4

Bits 0-7: priority for interrupt n.

PRI_5

Bits 8-15: priority for interrupt n.

PRI_6

Bits 16-23: priority for interrupt n.

PRI_7

Bits 24-31: priority for interrupt n.

IPR2

Interrupt Priority Register 2

Offset: 0x308, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_11 rw								PRI_10 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_9 rw								PRI_8 rw

Toggle Fields

PRI_8

Bits 0-7: priority for interrupt n.

PRI_9

Bits 8-15: priority for interrupt n.

PRI_10

Bits 16-23: priority for interrupt n.

PRI_11

Bits 24-31: priority for interrupt n.

IPR3

Interrupt Priority Register 3

Offset: 0x30C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_15 rw								PRI_14 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_13 rw								PRI_12 rw

Toggle Fields

PRI_12

Bits 0-7: priority for interrupt n.

PRI_13

Bits 8-15: priority for interrupt n.

PRI_14

Bits 16-23: priority for interrupt n.

PRI_15

Bits 24-31: priority for interrupt n.

IPR4

Interrupt Priority Register 4

Offset: 0x310, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_19 rw								PRI_18 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_17 rw								PRI_16 rw

Toggle Fields

PRI_16

Bits 0-7: priority for interrupt n.

PRI_17

Bits 8-15: priority for interrupt n.

PRI_18

Bits 16-23: priority for interrupt n.

PRI_19

Bits 24-31: priority for interrupt n.

IPR5

Interrupt Priority Register 5

Offset: 0x314, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_23 rw								PRI_22 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_21 rw								PRI_20 rw

Toggle Fields

PRI_20

Bits 0-7: priority for interrupt n.

PRI_21

Bits 8-15: priority for interrupt n.

PRI_22

Bits 16-23: priority for interrupt n.

PRI_23

Bits 24-31: priority for interrupt n.

IPR6

Interrupt Priority Register 6

Offset: 0x318, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_27 rw								PRI_26 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_25 rw								PRI_24 rw

Toggle Fields

PRI_24

Bits 0-7: priority for interrupt n.

PRI_25

Bits 8-15: priority for interrupt n.

PRI_26

Bits 16-23: priority for interrupt n.

PRI_27

Bits 24-31: priority for interrupt n.

IPR7

Interrupt Priority Register 7

Offset: 0x31C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_31 rw								PRI_30 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_29 rw								PRI_28 rw

Toggle Fields

PRI_28

Bits 0-7: priority for interrupt n.

PRI_29

Bits 8-15: priority for interrupt n.

PRI_30

Bits 16-23: priority for interrupt n.

PRI_31

Bits 24-31: priority for interrupt n.

PWR

0x40007000: Power control

12/164 fields covered. Toggle Registers

Show register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1		LPR				VOS		DBP			FPD_LPSLP	FPD_LPRUN	FPD_STOP	LPMS
0x4	CR2										PVDRT			PVDFT			PVDE
0x8	CR3	EIWUL					APC	ULPEN	RRS			EWUP6	EWUP5	EWUP4		EWUP2	EWUP1
0xC	CR4							VBRS	VBE			WP6	WP5	WP4		WP2	WP1
0x10	SR1	WUFI							SBF			WUF6	WUF5	WUF4		WUF2	WUF1
0x14	SR2					PVDO	VOSF	REGLPF	REGLPS	FLASH_RDY
0x18	SCR								CSBF			CWUF6	CWUF5	CWUF4		CWUF2	CWUF1
0x20	PUCRA	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x24	PDCRA	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x28	PUCRB	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x2C	PDCRB	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x30	PUCRC	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x34	PDCRC	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x38	PUCRD							PU9	PU8		PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x3C	PDCRD							PD9	PD8		PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x48	PUCRF														PU2	PU1	PU0
0x4C	PDCRF														PD2	PD1	PD0

CR1

Power control register 1

Offset: 0x0, reset: 0x00000200, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LPR rw				VOS rw		DBP rw			FPD_LPSLP rw	FPD_LPRUN rw	FPD_STOP rw	LPMS rw

Toggle Fields

LPMS

Bits 0-2: Low-power mode selection.

FPD_STOP

Bit 3: Flash memory powered down during Stop mode.

FPD_LPRUN

Bit 4: Flash memory powered down during Low-power run mode.

FPD_LPSLP

Bit 5: Flash memory powered down during Low-power sleep mode.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									PVDRT rw			PVDFT rw			PVDE rw

Toggle Fields

PVDE

Bit 0: Power voltage detector enable.

PVDFT

Bits 1-3: Power voltage detector falling threshold selection.

PVDRT

Bits 4-6: Power voltage detector rising threshold selection.

CR3

Power control register 3

Offset: 0x8, reset: 0X00008000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIWUL rw					APC rw	ULPEN rw	RRS rw			EWUP6 rw	EWUP5 rw	EWUP4 rw		EWUP2 rw	EWUP1 rw

Toggle Fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable WKUP5 wakeup pin.

EWUP6

Bit 5: Enable WKUP6 wakeup pin.

RRS

Bit 8: SRAM retention in Standby mode.

ULPEN

Bit 9: Enable the periodical sampling mode for PDR detection.

APC

Bit 10: Apply pull-up and pull-down configuration.

EIWUL

Bit 15: Enable internal wakeup line.

CR4

Power control register 4

Offset: 0xC, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						VBRS rw	VBE rw			WP6 rw	WP5 rw	WP4 rw		WP2 rw	WP1 rw

Toggle Fields

WP1

Bit 0: Wakeup pin WKUP1 polarity.

WP2

Bit 1: Wakeup pin WKUP2 polarity.

WP4

Bit 3: Wakeup pin WKUP4 polarity.

WP5

Bit 4: Wakeup pin WKUP5 polarity.

WP6

Bit 5: WKUP6 wakeup pin polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

SR1

Power status register 1

Offset: 0x10, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUFI r							SBF r			WUF6 r	WUF5 r	WUF4 r		WUF2 r	WUF1 r

Toggle Fields

WUF1

Bit 0: Wakeup flag 1.

WUF2

Bit 1: Wakeup flag 2.

WUF4

Bit 3: Wakeup flag 4.

WUF5

Bit 4: Wakeup flag 5.

WUF6

Bit 5: Wakeup flag 6.

SBF

Bit 8: Standby flag.

WUFI

Bit 15: Wakeup flag internal.

SR2

Power status register 2

Offset: 0x14, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PVDO r	VOSF r	REGLPF r	REGLPS r	FLASH_RDY r

Toggle Fields

FLASH_RDY

Bit 7: Flash ready flag.

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

SCR

Power status clear register

Offset: 0x18, reset: 0x00000000, access: write-only

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							CSBF w			CWUF6 w	CWUF5 w	CWUF4 w		CWUF2 w	CWUF1 w

Toggle Fields

CWUF1

Bit 0: Clear wakeup flag 1.

CWUF2

Bit 1: Clear wakeup flag 2.

CWUF4

Bit 3: Clear wakeup flag 4.

CWUF5

Bit 4: Clear wakeup flag 5.

CWUF6

Bit 5: Clear wakeup flag 6.

CSBF

Bit 8: Clear standby flag.

PUCRA

Power Port A pull-up control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU14

Bit 14: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD13

Bit 13: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PD15

Bit 15: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD4

Bit 4: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PU9 rw	PU8 rw		PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PD9 rw	PD8 rw		PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PUCRF

Power Port F pull-up control register

Offset: 0x48, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PU2 rw	PU1 rw	PU0 rw

Toggle Fields

PU0

Bit 0: Port F pull-up bit y (y=0..15).

PU1

Bit 1: Port F pull-up bit y (y=0..15).

PU2

Bit 2: Port F pull-up bit y (y=0..15).

PDCRF

Power Port F pull-down control register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PD2 rw	PD1 rw	PD0 rw

Toggle Fields

PD0

Bit 0: Port F pull-down bit y (y=0..15).

PD1

Bit 1: Port F pull-down bit y (y=0..15).

PD2

Bit 2: Port F pull-down bit y (y=0..15).

RCC

0x40021000: Reset and clock control

10/191 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR							PLLRDY	PLLON					CSSON	HSEBYP	HSERDY	HSEON			HSIDIV			HSIRDY	HSIKERON	HSION
0x4	ICSCR																		HSITRIM							HSICAL
0x8	CFGR		MCOPRE				MCOSEL												PPRE			HPRE						SWS			SW
0xC	PLLSYSCFGR	PLLR			PLLREN	PLLQ			PLLQEN			PLLP					PLLPEN		PLLN								PLLM					PLLSRC
0x18	CIER																											PLLSYSRDYIE	HSERDYIE	HSIRDYIE		LSERDYIE	LSIRDYIE
0x1C	CIFR																							LSECSSF	CSSF			PLLSYSRDYF	HSERDYF	HSIRDYF		LSERDYF	LSIRDYF
0x20	CICR																							LSECSSC	CSSC			PLLSYSRDYC	HSERDYC	HSIRDYC		LSERDYC	LSIRDYC
0x24	IOPRSTR																											IOPFRST		IOPDRST	IOPCRST	IOPBRST	IOPARST
0x28	AHBRSTR																				CRCRST				FLASHRST								DMARST
0x2C	APBRSTR1	LPTIM1RST	LPTIM2RST	DAC1RST	PWRRST	DBGRST	UCPD2RST	UCPD1RST	CECRST		I2C2RST	I2C1RST	LPUART1RST	USART4RST	USART3RST	USART2RST			SPI2RST									TIM7RST	TIM6RST			TIM3RST	TIM2RST
0x30	APBRSTR2												ADCRST		TIM17RST	TIM16RST	TIM15RST	TIM14RST	USART1RST		SPI1RST	TIM1RST											SYSCFGRST
0x34	IOPENR																											IOPFEN		IOPDEN	IOPCEN	IOPBEN	IOPAEN
0x38	AHBENR																				CRCEN				FLASHEN								DMAEN
0x3C	APBENR1	LPTIM1EN	LPTIM2EN	DAC1EN	PWREN	DBGEN	UCPD2EN	UCPD1EN	CECEN		I2C2EN	I2C1EN	LPUART1EN	USART4EN	USART3EN	USART2EN			SPI2EN			WWDGEN	RTCAPBEN					TIM7EN	TIM6EN			TIM3EN	TIM2EN
0x40	APBENR2												ADCEN		TIM17EN	TIM16EN	TIM15EN	TIM14EN	USART1EN		SPI1EN	TIM1EN											SYSCFGEN
0x44	IOPSMENR																											IOPFSMEN		IOPDSMEN	IOPCSMEN	IOPBSMEN	IOPASMEN
0x48	AHBSMENR																				CRCSMEN			SRAMSMEN	FLASHSMEN								DMASMEN
0x4C	APBSMENR1	LPTIM1SMEN	LPTIM2SMEN	DAC1SMEN	PWRSMEN	DBGSMEN	UCPD2SMEN	UCPD1SMEN	CECSMEN		I2C2SMEN	I2C1SMEN	LPUART1SMEN	USART4SMEN	USART3SMEN	USART2SMEN			SPI2SMEN			WWDGSMEN	RTCAPBSMEN					TIM7SMEN	TIM6SMEN			TIM3SMEN	TIM2SMEN
0x50	APBSMENR2												ADCSMEN		TIM17SMEN	TIM16SMEN	TIM15SMEN	TIM14SMEN	USART1SMEN		SPI1SMEN	TIM1SMEN											SYSCFGSMEN
0x54	CCIPR	ADCSEL							TIM15SEL		TIM1SEL	LPTIM2SEL		LPTIM1SEL				I2S2SEL		I2C1SEL		LPUART1SEL					CECSEL			USART2SEL		USART1SEL
0x5C	BDCR							LSCOSEL	LSCOEN								BDRST	RTCEN						RTCSEL			LSECSSD	LSECSSON	LSEDRV		LSEBYP	LSERDY	LSEON
0x60	CSR	LPWRRSTF	WWDGRSTF	IWDGRSTF	SFTRSTF	PWRRSTF	PINRSTF	OBLRSTF		RMVF																						LSIRDY	LSION

CR

Clock control register

Offset: 0x0, reset: 0x00000063, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						PLLRDY rw	PLLON rw					CSSON rw	HSEBYP rw	HSERDY rw	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		HSIDIV rw			HSIRDY rw	HSIKERON rw	HSION rw

Toggle Fields

HSION

Bit 8: HSI16 clock enable.

HSIKERON

Bit 9: HSI16 always enable for peripheral kernels.

HSIRDY

Bit 10: HSI16 clock ready flag.

HSIDIV

Bits 11-13: HSI16 clock division factor.

HSEON

Bit 16: HSE clock enable.

HSERDY

Bit 17: HSE clock ready flag.

HSEBYP

Bit 18: HSE crystal oscillator bypass.

CSSON

Bit 19: Clock security system enable.

PLLON

Bit 24: PLL enable.

PLLRDY

Bit 25: PLL clock ready flag.

ICSCR

Internal clock sources calibration register

Offset: 0x4, reset: 0x10000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	HSITRIM rw							HSICAL r

Toggle Fields

HSICAL

Bits 0-7: HSI16 clock calibration.

HSITRIM

Bits 8-14: HSI16 clock trimming.

CFGR

Clock configuration register

Offset: 0x8, reset: 0x00000000, access: Unspecified

2/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	MCOPRE r				MCOSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PPRE rw			HPRE rw						SWS r			SW rw

Toggle Fields

SW

Bits 0-2: System clock switch.

SWS

Bits 3-5: System clock switch status.

HPRE

Bits 8-11: AHB prescaler.

PPRE

Bits 12-14: APB prescaler.

MCOSEL

Bits 24-26: Microcontroller clock output.

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

PLLSYSCFGR

PLL configuration register

Offset: 0xC, reset: 0x00001000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PLLR rw			PLLREN rw	PLLQ rw			PLLQEN rw			PLLP rw					PLLPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PLLN rw								PLLM rw					PLLSRC rw

Toggle Fields

PLLSRC

Bits 0-1: PLL input clock source.

PLLM

Bits 4-6: Division factor M of the PLL input clock divider.

PLLN

Bits 8-14: PLL frequency multiplication factor N.

PLLPEN

Bit 16: PLLPCLK clock output enable.

PLLP

Bits 17-21: PLL VCO division factor P for PLLPCLK clock output.

PLLQEN

Bit 24: PLLQCLK clock output enable.

PLLQ

Bits 25-27: PLL VCO division factor Q for PLLQCLK clock output.

PLLREN

Bit 28: PLLRCLK clock output enable.

PLLR

Bits 29-31: PLL VCO division factor R for PLLRCLK clock output.

CIER

Clock interrupt enable register

Offset: 0x18, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										PLLSYSRDYIE rw	HSERDYIE rw	HSIRDYIE rw		LSERDYIE rw	LSIRDYIE rw

Toggle Fields

LSIRDYIE

Bit 0: LSI ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLSYSRDYIE

Bit 5: PLL ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1C, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						LSECSSF r	CSSF r			PLLSYSRDYF r	HSERDYF r	HSIRDYF r		LSERDYF r	LSIRDYF r

Toggle Fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLSYSRDYF

Bit 5: PLL ready interrupt flag.

CSSF

Bit 8: Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, reset: 0x00000000, access: write-only

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						LSECSSC w	CSSC w			PLLSYSRDYC w	HSERDYC w	HSIRDYC w		LSERDYC w	LSIRDYC w

Toggle Fields

LSIRDYC

Bit 0: LSI ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLSYSRDYC

Bit 5: PLL ready interrupt clear.

CSSC

Bit 8: Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

IOPRSTR

GPIO reset register

Offset: 0x24, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IOPFRST rw		IOPDRST rw	IOPCRST rw	IOPBRST rw	IOPARST rw

Toggle Fields

IOPARST

Bit 0: I/O port A reset.

IOPBRST

Bit 1: I/O port B reset.

IOPCRST

Bit 2: I/O port C reset.

IOPDRST

Bit 3: I/O port D reset.

IOPFRST

Bit 5: I/O port F reset.

AHBRSTR

AHB peripheral reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCRST rw				FLASHRST rw								DMARST rw

Toggle Fields

DMARST

Bit 0: DMA1 reset.

FLASHRST

Bit 8: FLITF reset.

CRCRST

Bit 12: CRC reset.

APBRSTR1

APB peripheral reset register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1RST rw	LPTIM2RST rw	DAC1RST rw	PWRRST rw	DBGRST rw	UCPD2RST rw	UCPD1RST rw	CECRST rw		I2C2RST rw	I2C1RST rw	LPUART1RST rw	USART4RST rw	USART3RST rw	USART2RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2RST rw									TIM7RST rw	TIM6RST rw			TIM3RST rw	TIM2RST rw

Toggle Fields

TIM2RST

Bit 0: TIM2 timer reset.

TIM3RST

Bit 1: TIM3 timer reset.

TIM6RST

Bit 4: TIM6 timer reset.

TIM7RST

Bit 5: TIM7 timer reset.

SPI2RST

Bit 14: SPI2 reset.

USART2RST

Bit 17: USART2 reset.

USART3RST

Bit 18: USART3 reset.

USART4RST

Bit 19: USART4 reset.

LPUART1RST

Bit 20: LPUART1 reset.

I2C1RST

Bit 21: I2C1 reset.

I2C2RST

Bit 22: I2C2 reset.

CECRST

Bit 24: HDMI CEC reset.

UCPD1RST

Bit 25: UCPD1 reset.

UCPD2RST

Bit 26: UCPD2 reset.

DBGRST

Bit 27: Debug support reset.

PWRRST

Bit 28: Power interface reset.

DAC1RST

Bit 29: DAC1 interface reset.

LPTIM2RST

Bit 30: Low Power Timer 2 reset.

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

APBRSTR2

APB peripheral reset register 2

Offset: 0x30, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADCRST rw		TIM17RST rw	TIM16RST rw	TIM15RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIM14RST rw	USART1RST rw		SPI1RST rw	TIM1RST rw											SYSCFGRST rw

Toggle Fields

SYSCFGRST

Bit 0: SYSCFG, COMP and VREFBUF reset.

TIM1RST

Bit 11: TIM1 timer reset.

SPI1RST

Bit 12: SPI1 reset.

USART1RST

Bit 14: USART1 reset.

TIM14RST

Bit 15: TIM14 timer reset.

TIM15RST

Bit 16: TIM15 timer reset.

TIM16RST

Bit 17: TIM16 timer reset.

TIM17RST

Bit 18: TIM17 timer reset.

ADCRST

Bit 20: ADC reset.

IOPENR

GPIO clock enable register

Offset: 0x34, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IOPFEN rw		IOPDEN rw	IOPCEN rw	IOPBEN rw	IOPAEN rw

Toggle Fields

IOPAEN

Bit 0: I/O port A clock enable.

IOPBEN

Bit 1: I/O port B clock enable.

IOPCEN

Bit 2: I/O port C clock enable.

IOPDEN

Bit 3: I/O port D clock enable.

IOPFEN

Bit 5: I/O port F clock enable.

AHBENR

AHB peripheral clock enable register

Offset: 0x38, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw				FLASHEN rw								DMAEN rw

Toggle Fields

DMAEN

Bit 0: DMA clock enable.

FLASHEN

Bit 8: Flash memory interface clock enable.

CRCEN

Bit 12: CRC clock enable.

APBENR1

APB peripheral clock enable register 1

Offset: 0x3C, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1EN rw	LPTIM2EN rw	DAC1EN rw	PWREN rw	DBGEN rw	UCPD2EN rw	UCPD1EN rw	CECEN rw		I2C2EN rw	I2C1EN rw	LPUART1EN rw	USART4EN rw	USART3EN rw	USART2EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2EN rw			WWDGEN rw	RTCAPBEN rw					TIM7EN rw	TIM6EN rw			TIM3EN rw	TIM2EN rw

Toggle Fields

TIM2EN

Bit 0: TIM2 timer clock enable.

TIM3EN

Bit 1: TIM3 timer clock enable.

TIM6EN

Bit 4: TIM6 timer clock enable.

TIM7EN

Bit 5: TIM7 timer clock enable.

RTCAPBEN

Bit 10: RTC APB clock enable.

WWDGEN

Bit 11: WWDG clock enable.

SPI2EN

Bit 14: SPI2 clock enable.

USART2EN

Bit 17: USART2 clock enable.

USART3EN

Bit 18: USART3 clock enable.

USART4EN

Bit 19: USART4 clock enable.

LPUART1EN

Bit 20: LPUART1 clock enable.

I2C1EN

Bit 21: I2C1 clock enable.

I2C2EN

Bit 22: I2C2 clock enable.

CECEN

Bit 24: HDMI CEC clock enable.

UCPD1EN

Bit 25: UCPD1 clock enable.

UCPD2EN

Bit 26: UCPD2 clock enable.

DBGEN

Bit 27: Debug support clock enable.

PWREN

Bit 28: Power interface clock enable.

DAC1EN

Bit 29: DAC1 interface clock enable.

LPTIM2EN

Bit 30: LPTIM2 clock enable.

LPTIM1EN

Bit 31: LPTIM1 clock enable.

APBENR2

APB peripheral clock enable register 2

Offset: 0x40, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADCEN rw		TIM17EN rw	TIM16EN rw	TIM15EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIM14EN rw	USART1EN rw		SPI1EN rw	TIM1EN rw											SYSCFGEN rw

Toggle Fields

SYSCFGEN

Bit 0: SYSCFG, COMP and VREFBUF clock enable.

TIM1EN

Bit 11: TIM1 timer clock enable.

SPI1EN

Bit 12: SPI1 clock enable.

USART1EN

Bit 14: USART1 clock enable.

TIM14EN

Bit 15: TIM14 timer clock enable.

TIM15EN

Bit 16: TIM15 timer clock enable.

TIM16EN

Bit 17: TIM16 timer clock enable.

TIM17EN

Bit 18: TIM16 timer clock enable.

ADCEN

Bit 20: ADC clock enable.

IOPSMENR

GPIO in Sleep mode clock enable register

Offset: 0x44, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IOPFSMEN rw		IOPDSMEN rw	IOPCSMEN rw	IOPBSMEN rw	IOPASMEN rw

Toggle Fields

IOPASMEN

Bit 0: I/O port A clock enable during Sleep mode.

IOPBSMEN

Bit 1: I/O port B clock enable during Sleep mode.

IOPCSMEN

Bit 2: I/O port C clock enable during Sleep mode.

IOPDSMEN

Bit 3: I/O port D clock enable during Sleep mode.

IOPFSMEN

Bit 5: I/O port F clock enable during Sleep mode.

AHBSMENR

AHB peripheral clock enable in Sleep mode register

Offset: 0x48, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCSMEN rw			SRAMSMEN rw	FLASHSMEN rw								DMASMEN rw

Toggle Fields

DMASMEN

Bit 0: DMA clock enable during Sleep mode.

FLASHSMEN

Bit 8: Flash memory interface clock enable during Sleep mode.

SRAMSMEN

Bit 9: SRAM clock enable during Sleep mode.

CRCSMEN

Bit 12: CRC clock enable during Sleep mode.

APBSMENR1

APB peripheral clock enable in Sleep mode register 1

Offset: 0x4C, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1SMEN rw	LPTIM2SMEN rw	DAC1SMEN rw	PWRSMEN rw	DBGSMEN rw	UCPD2SMEN rw	UCPD1SMEN rw	CECSMEN rw		I2C2SMEN rw	I2C1SMEN rw	LPUART1SMEN rw	USART4SMEN rw	USART3SMEN rw	USART2SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2SMEN rw			WWDGSMEN rw	RTCAPBSMEN rw					TIM7SMEN rw	TIM6SMEN rw			TIM3SMEN rw	TIM2SMEN rw

Toggle Fields

TIM2SMEN

Bit 0: TIM2 timer clock enable during Sleep mode.

TIM3SMEN

Bit 1: TIM3 timer clock enable during Sleep mode.

TIM6SMEN

Bit 4: TIM6 timer clock enable during Sleep mode.

TIM7SMEN

Bit 5: TIM7 timer clock enable during Sleep mode.

RTCAPBSMEN

Bit 10: RTC APB clock enable during Sleep mode.

WWDGSMEN

Bit 11: WWDG clock enable during Sleep mode.

SPI2SMEN

Bit 14: SPI2 clock enable during Sleep mode.

USART2SMEN

Bit 17: USART2 clock enable during Sleep mode.

USART3SMEN

Bit 18: USART3 clock enable during Sleep mode.

USART4SMEN

Bit 19: USART4 clock enable during Sleep mode.

LPUART1SMEN

Bit 20: LPUART1 clock enable during Sleep mode.

I2C1SMEN

Bit 21: I2C1 clock enable during Sleep mode.

I2C2SMEN

Bit 22: I2C2 clock enable during Sleep mode.

CECSMEN

Bit 24: HDMI CEC clock enable during Sleep mode.

UCPD1SMEN

Bit 25: UCPD1 clock enable during Sleep mode.

UCPD2SMEN

Bit 26: UCPD2 clock enable during Sleep mode.

DBGSMEN

Bit 27: Debug support clock enable during Sleep mode.

PWRSMEN

Bit 28: Power interface clock enable during Sleep mode.

DAC1SMEN

Bit 29: DAC1 interface clock enable during Sleep mode.

LPTIM2SMEN

Bit 30: Low Power Timer 2 clock enable during Sleep mode.

LPTIM1SMEN

Bit 31: Low Power Timer 1 clock enable during Sleep mode.

APBSMENR2

APB peripheral clock enable in Sleep mode register 2

Offset: 0x50, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADCSMEN rw		TIM17SMEN rw	TIM16SMEN rw	TIM15SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIM14SMEN rw	USART1SMEN rw		SPI1SMEN rw	TIM1SMEN rw											SYSCFGSMEN rw

Toggle Fields

SYSCFGSMEN

Bit 0: SYSCFG, COMP and VREFBUF clock enable during Sleep mode.

TIM1SMEN

Bit 11: TIM1 timer clock enable during Sleep mode.

SPI1SMEN

Bit 12: SPI1 clock enable during Sleep mode.

USART1SMEN

Bit 14: USART1 clock enable during Sleep mode.

TIM14SMEN

Bit 15: TIM14 timer clock enable during Sleep mode.

TIM15SMEN

Bit 16: TIM15 timer clock enable during Sleep mode.

TIM16SMEN

Bit 17: TIM16 timer clock enable during Sleep mode.

TIM17SMEN

Bit 18: TIM16 timer clock enable during Sleep mode.

ADCSMEN

Bit 20: ADC clock enable during Sleep mode.

CCIPR

Peripherals independent clock configuration register

Offset: 0x54, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCSEL rw							TIM15SEL rw		TIM1SEL rw	LPTIM2SEL rw		LPTIM1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I2S2SEL rw		I2C1SEL rw		LPUART1SEL rw					CECSEL rw			USART2SEL rw		USART1SEL rw

Toggle Fields

USART1SEL

Bits 0-1: USART1 clock source selection.

USART2SEL

Bits 2-3: USART2 clock source selection.

CECSEL

Bit 6: HDMI CEC clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2S2SEL

Bits 14-15: I2S1 clock source selection.

LPTIM1SEL

Bits 18-19: LPTIM1 clock source selection.

LPTIM2SEL

Bits 20-21: LPTIM2 clock source selection.

TIM1SEL

Bit 22: TIM1 clock source selection.

TIM15SEL

Bit 24: TIM15 clock source selection.

ADCSEL

Bits 30-31: ADCs clock source selection.

BDCR

RTC domain control register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						LSCOSEL rw	LSCOEN rw								BDRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTCEN rw						RTCSEL rw			LSECSSD rw	LSECSSON rw	LSEDRV rw		LSEBYP rw	LSERDY rw	LSEON rw

Toggle Fields

LSEON

Bit 0: LSE oscillator enable.

LSERDY

Bit 1: LSE oscillator ready.

LSEBYP

Bit 2: LSE oscillator bypass.

LSEDRV

Bits 3-4: LSE oscillator drive capability.

LSECSSON

Bit 5: CSS on LSE enable.

LSECSSD

Bit 6: CSS on LSE failure Detection.

RTCSEL

Bits 8-9: RTC clock source selection.

RTCEN

Bit 15: RTC clock enable.

BDRST

Bit 16: RTC domain software reset.

LSCOEN

Bit 24: Low-speed clock output (LSCO) enable.

LSCOSEL

Bit 25: Low-speed clock output selection.

CSR

Control/status register

Offset: 0x60, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPWRRSTF rw	WWDGRSTF rw	IWDGRSTF rw	SFTRSTF rw	PWRRSTF rw	PINRSTF rw	OBLRSTF rw		RMVF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														LSIRDY rw	LSION rw

Toggle Fields

LSION

Bit 0: LSI oscillator enable.

LSIRDY

Bit 1: LSI oscillator ready.

RMVF

Bit 23: Remove reset flags.

OBLRSTF

Bit 25: Option byte loader reset flag.

PINRSTF

Bit 26: Pin reset flag.

PWRRSTF

Bit 27: BOR or POR/PDR flag.

SFTRSTF

Bit 28: Software reset flag.

IWDGRSTF

Bit 29: Independent window watchdog reset flag.

WWDGRSTF

Bit 30: Window watchdog reset flag.

LPWRRSTF

Bit 31: Low-power reset flag.

RTC

0x40002800: Real-time clock

36/133 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	TR									PM	HT		HU					MNT			MNU					ST			SU
0x4	DR								YT				YU				WDU			MT	MU						DT		DU
0x8	SSR																SS
0xC	ICSR															RECALPF									INIT	INITF	RSF	INITS	SHPF	WUTWF	ALRBWF	ALRAWF
0x10	PRER									PREDIV_A								PREDIV_S
0x14	WUTR																WUT
0x18	CR	OUT2EN	TAMPALRM_TYPE	TAMPALRM_PU		TAMPOE	TAMPTS	ITSE	COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H	TSIE	WUTIE	ALRBIE	ALRAIE	TSE	WUTE	ALRBE	ALRAE		FMT	BYPSHAD	REFCKON	TSEDGE	WUCKSEL
0x24	WPR																								KEY
0x28	CALR																CALP	CALW8	CALW16					CALM
0x2C	SHIFTR	ADD1S																SUBFS
0x30	TSTR									PM	HT		HU					MNT			MNU					ST			SU
0x34	TSDR																WDU			MT	MU						DT		DU
0x38	TSSSR																SS
0x40	ALRMAR	MSK4	WDSEL	DT	DU				MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x44	ALRMASSR				MASKSS													SS
0x48	ALRMBR	MSK4	WDSEL	DT	DU				MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x4C	ALRMBSSR				MASKSS													SS
0x50	SR																										ITSF	TSOVF	TSF	WUTF	ALRBF	ALRAF
0x54	MISR																										ITSMF	TSOVMF	TSMF	WUTMF	ALRBMF	ALRAMF
0x5C	SCR																										CITSF	CTSOVF	CTSF	CWUTF	CALRBF	CALRAF
0x3F0	HWCFGR				TRUST_ZONE				OPTIONREG_OUT								TIMESTAMP				SMOOTH_CALIB				WAKEUP				ALARMB
0x3F4	VERR																								MAJREV				MINREV
0x3F8	IPIDR	IPID															IPID
0x3FC	SIDR	SID															SID

TR

time register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle Fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle Fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

SSR

sub second register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle Fields

SS

Bits 0-15: Sub second value.

ICSR

initialization and status register

Offset: 0xC, reset: 0x00000007, access: Unspecified

6/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RECALPF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								INIT rw	INITF r	RSF rw	INITS r	SHPF rw	WUTWF r	ALRBWF r	ALRAWF r

Toggle Fields

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

Toggle Fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

Toggle Fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

CR

control register

Offset: 0x18, reset: 0x00000000, access: read-write

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OUT2EN rw	TAMPALRM_TYPE rw	TAMPALRM_PU rw			TAMPOE rw	TAMPTS rw	ITSE rw	COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H rw	ADD1H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE rw	WUTIE rw	ALRBIE rw	ALRAIE rw	TSE rw	WUTE rw	ALRBE rw	ALRAE rw		FMT rw	BYPSHAD rw	REFCKON rw	TSEDGE rw	WUCKSEL rw

Toggle Fields

WUCKSEL

Bits 0-2: WUCKSEL.

TSEDGE

Bit 3: TSEDGE.

REFCKON

Bit 4: REFCKON.

BYPSHAD

Bit 5: BYPSHAD.

FMT

Bit 6: FMT.

ALRAE

Bit 8: ALRAE.

ALRBE

Bit 9: ALRBE.

WUTE

Bit 10: WUTE.

TSE

Bit 11: TSE.

ALRAIE

Bit 12: ALRAIE.

ALRBIE

Bit 13: ALRBIE.

WUTIE

Bit 14: WUTIE.

TSIE

Bit 15: TSIE.

ADD1H

Bit 16: ADD1H.

SUB1H

Bit 17: SUB1H.

BKP

Bit 18: BKP.

COSEL

Bit 19: COSEL.

POL

Bit 20: POL.

OSEL

Bits 21-22: OSEL.

COE

Bit 23: COE.

ITSE

Bit 24: ITSE.

TAMPTS

Bit 25: TAMPTS.

TAMPOE

Bit 26: TAMPOE.

TAMPALRM_PU

Bit 29: TAMPALRM_PU.

TAMPALRM_TYPE

Bit 30: TAMPALRM_TYPE.

OUT2EN

Bit 31: OUT2EN.

WPR

write protection register

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle Fields

KEY

Bits 0-7: Write protection key.

CALR

calibration register

Offset: 0x28, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw					CALM rw

Toggle Fields

CALM

Bits 0-8: Calibration minus.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

SHIFTR

shift control register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

Toggle Fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM r	HT r		HU r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT r			MNU r					ST r			SU r

Toggle Fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU r			MT r	MU r						DT r		DU r

Toggle Fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

timestamp sub second register

Offset: 0x38, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle Fields

SS

Bits 0-15: Sub second value.

ALRMAR

alarm A register

Offset: 0x40, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle Fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMASSR

alarm A sub second register

Offset: 0x44, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle Fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRMBR

alarm B register

Offset: 0x48, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle Fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm B seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm B minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm B hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm B date mask.

ALRMBSSR

alarm B sub second register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle Fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

SR

status register

Offset: 0x50, reset: 0x00000000, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ITSF r	TSOVF r	TSF r	WUTF r	ALRBF r	ALRAF r

Toggle Fields

ALRAF

Bit 0: ALRAF.

ALRBF

Bit 1: ALRBF.

WUTF

Bit 2: WUTF.

TSF

Bit 3: TSF.

TSOVF

Bit 4: TSOVF.

ITSF

Bit 5: ITSF.

MISR

masked interrupt status register

Offset: 0x54, reset: 0x00000000, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ITSMF r	TSOVMF r	TSMF r	WUTMF r	ALRBMF r	ALRAMF r

Toggle Fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SCR

status clear register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CITSF rw	CTSOVF rw	CTSF rw	CWUTF rw	CALRBF rw	CALRAF rw

Toggle Fields

CALRAF

Bit 0: CALRAF.

CALRBF

Bit 1: CALRBF.

CWUTF

Bit 2: CWUTF.

CTSF

Bit 3: CTSF.

CTSOVF

Bit 4: CTSOVF.

CITSF

Bit 5: CITSF.

HWCFGR

hardware configuration register

Offset: 0x3F0, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TRUST_ZONE rw				OPTIONREG_OUT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMESTAMP rw				SMOOTH_CALIB rw				WAKEUP rw				ALARMB rw

Toggle Fields

ALARMB

Bits 0-3: ALARMB.

WAKEUP

Bits 4-7: WAKEUP.

SMOOTH_CALIB

Bits 8-11: SMOOTH_CALIB.

TIMESTAMP

Bits 12-15: TIMESTAMP.

OPTIONREG_OUT

Bits 16-23: OPTIONREG_OUT.

TRUST_ZONE

Bits 24-27: TRUST_ZONE.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0x00000010, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3F8, reset: 0x00120033, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size Identification.

SCB

0xE000ED00: System control block

5/31 fields covered. Toggle Registers

Show register map

Offset	Name	31	28	27	26	25	23	22	19	18	15	11	9	8	4	3	2	1	0
0x0	CPUID	Implementer					Variant		Architecture		PartNo					Revision
0x4	ICSR	NMIPENDSET	PENDSVSET	PENDSVCLR	PENDSTSET	PENDSTCLR		ISRPENDING		VECTPENDING	VECTPENDING	RETTOBASE		VECTACTIVE
0x8	VTOR	TBLOFF									TBLOFF
0xC	AIRCR	VECTKEYSTAT									ENDIANESS						SYSRESETREQ	VECTCLRACTIVE
0x10	SCR														SEVEONPEND		SLEEPDEEP	SLEEPONEXIT
0x14	CCR												STKALIGN	BFHFNMIGN	DIV_0_TRP	UNALIGN__TRP		USERSETMPEND	NONBASETHRDENA
0x1C	SHPR2	PRI_11
0x20	SHPR3	PRI_15					PRI_14

CPUID

CPUID base register

Offset: 0x0, reset: 0x410FC241, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Implementer r								Variant r				Architecture r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PartNo r												Revision r

Toggle Fields

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Architecture

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NMIPENDSET rw			PENDSVSET rw	PENDSVCLR rw	PENDSTSET rw	PENDSTCLR rw			ISRPENDING rw				VECTPENDING rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VECTPENDING rw				RETTOBASE rw			VECTACTIVE rw

Toggle Fields

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TBLOFF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TBLOFF rw

Toggle Fields

TBLOFF

Bits 7-31: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VECTKEYSTAT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ENDIANESS rw													SYSRESETREQ rw	VECTCLRACTIVE rw

Toggle Fields

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											SEVEONPEND rw		SLEEPDEEP rw	SLEEPONEXIT rw

Toggle Fields

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						STKALIGN rw	BFHFNMIGN rw				DIV_0_TRP rw	UNALIGN__TRP rw		USERSETMPEND rw	NONBASETHRDENA rw

Toggle Fields

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR2

System handler priority registers

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_11 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_15 rw								PRI_14 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SPI1

0x40013000: Serial peripheral interface/Inter-IC sound

21/61 fields covered. Toggle Registers

Show register map

Offset	Name	31	19	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1			BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4	CR2				LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8	SR						FTLVL		FRLVL		TIFRFE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xC	DR			DR
0x10	CRCPR			CRCPOLY
0x14	RXCRCR			RxCRC
0x18	TXCRCR			TxCRC
0x1C	I2SCFGR							I2SMOD	SE2	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20	I2SPR									MCKOE	ODD	I2SDIV
0x3F0	HWCFGR		NSSCFG	DSCFG				I2SCKCFG				I2SCFG				CRCCFG
0x3F4	VERR											MAJREV				MINREV
0x3F8	IPIDR	IPID		IPID
0x3FC	SIDR	SID		SID

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle Fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle Fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

10/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		TIFRFE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle Fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle Fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle Fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle Fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle Fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	SE2 rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle Fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Inactive state clock polarity.

I2SSTD

Bits 4-5: standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

SE2

Bit 10: I2S enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

prescaler register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle Fields

I2SDIV

Bits 0-7: linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

HWCFGR

hardware configuration register

Offset: 0x3F0, reset: 0x0000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												NSSCFG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DSCFG r				I2SCKCFG r				I2SCFG r				CRCCFG r

Toggle Fields

CRCCFG

Bits 0-3: CRC capable at SPI mode.

I2SCFG

Bits 4-7: I2S mode implementation.

I2SCKCFG

Bits 8-11: I2S master clock generator at I2S mode.

DSCFG

Bits 12-15: SPI data size configuration.

NSSCFG

Bits 16-19: NSS pulse feature enhancement at SPI master.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3F8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3FC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size Identification.

SPI2

0x40003800: Serial peripheral interface/Inter-IC sound

21/61 fields covered. Toggle Registers

Show register map

Offset	Name	31	19	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1			BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4	CR2				LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8	SR						FTLVL		FRLVL		TIFRFE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xC	DR			DR
0x10	CRCPR			CRCPOLY
0x14	RXCRCR			RxCRC
0x18	TXCRCR			TxCRC
0x1C	I2SCFGR							I2SMOD	SE2	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20	I2SPR									MCKOE	ODD	I2SDIV
0x3F0	HWCFGR		NSSCFG	DSCFG				I2SCKCFG				I2SCFG				CRCCFG
0x3F4	VERR											MAJREV				MINREV
0x3F8	IPIDR	IPID		IPID
0x3FC	SIDR	SID		SID

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle Fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle Fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

10/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		TIFRFE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle Fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle Fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle Fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle Fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle Fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	SE2 rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle Fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Inactive state clock polarity.

I2SSTD

Bits 4-5: standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

SE2

Bit 10: I2S enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

prescaler register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle Fields

I2SDIV

Bits 0-7: linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

HWCFGR

hardware configuration register

Offset: 0x3F0, reset: 0x0000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												NSSCFG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DSCFG r				I2SCKCFG r				I2SCFG r				CRCCFG r

Toggle Fields

CRCCFG

Bits 0-3: CRC capable at SPI mode.

I2SCFG

Bits 4-7: I2S mode implementation.

I2SCKCFG

Bits 8-11: I2S master clock generator at I2S mode.

DSCFG

Bits 12-15: SPI data size configuration.

NSSCFG

Bits 16-19: NSS pulse feature enhancement at SPI master.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3F8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3FC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size Identification.

STK

0xE000E010: SysTick timer

0/9 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	23	16	15	2	1	0
0x0	CSR				COUNTFLAG		CLKSOURCE	TICKINT	ENABLE
0x4	RVR			RELOAD		RELOAD
0x8	CVR			CURRENT		CURRENT
0xC	CALIB	NOREF	SKEW	TENMS		TENMS

CSR

SysTick control and status register

Offset: 0x0, reset: 0X00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															COUNTFLAG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLKSOURCE rw	TICKINT rw	ENABLE rw

Toggle Fields

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

RVR

SysTick reload value register

Offset: 0x4, reset: 0X00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								RELOAD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle Fields

RELOAD

Bits 0-23: RELOAD value.

CVR

SysTick current value register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CURRENT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CURRENT rw

Toggle Fields

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NOREF rw	SKEW rw							TENMS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TENMS rw

Toggle Fields

TENMS

Bits 0-23: Calibration value.

SKEW

Bit 30: SKEW flag: Indicates whether the TENMS value is exact.

NOREF

Bit 31: NOREF flag. Reads as zero.

SYSCFG_VREFBUF

0x40010000: System configuration controller

65/85 fields covered. Toggle Registers

Show register map

Offset	Name	23	21	20	19	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CFGR1	I2C_PAx_FMP	I2C2_FMP	I2C1_FMP	I2C_PBx_FMP		UCPD2_STROBE	UCPD1_STROBE	BOOSTEN	IR_MOD		IR_POL	PA11_PA12_RMP			MEM_MODE
0x18	CFGR2								SRAM_PEF					ECC_LOCK	PVD_LOCK	SRAM_PARITY_LOCK	LOCKUP_LOCK
0x30	VREFBUF_CSR										VRS			VRR		HIZ	ENVR
0x34	VREFBUF_CCR											TRIM
0x80	ITLINE0																WWDG
0x84	ITLINE1																PVDOUT
0x88	ITLINE2															RTC	TAMP
0x8C	ITLINE3															FLASH_ECC	FLASH_ITF
0x90	ITLINE4																RCC
0x94	ITLINE5															EXTI1	EXTI0
0x98	ITLINE6															EXTI3	EXTI2
0x9C	ITLINE7					EXTI15	EXTI14	EXTI13	EXTI12	EXTI11	EXTI10	EXTI9	EXTI8	EXTI7	EXTI6	EXTI5	EXTI4
0xA0	ITLINE8															UCPD2	UCPD1
0xA4	ITLINE9																DMA1_CH1
0xA8	ITLINE10															DMA1_CH3	DMA1_CH2
0xAC	ITLINE11												DMA1_CH7	DMA1_CH6	DMA1_CH5	DMA1_CH4	DMAMUX
0xB0	ITLINE12														COMP2	COMP1	ADC
0xB4	ITLINE13													TIM1_BRK	TIM1_UPD	TIM1_TRG	TIM1_CCU
0xB8	ITLINE14																TIM1_CC
0xBC	ITLINE15																TIM2
0xC0	ITLINE16																TIM3
0xC4	ITLINE17														LPTIM1	DAC	TIM6
0xC8	ITLINE18															LPTIM2	TIM7
0xCC	ITLINE19																TIM14
0xD0	ITLINE20																TIM15
0xD4	ITLINE21																TIM16
0xD8	ITLINE22																TIM17
0xDC	ITLINE23																I2C1
0xE0	ITLINE24																I2C2
0xE4	ITLINE25																SPI1
0xE8	ITLINE26																SPI2
0xEC	ITLINE27																USART1
0xF0	ITLINE28																USART2
0xF4	ITLINE29														USART5	USART4	USART3
0xF8	ITLINE30																USART2
0xFC	ITLINE31															AES	RNG

CFGR1

SYSCFG configuration register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								I2C_PAx_FMP rw		I2C2_FMP rw	I2C1_FMP rw	I2C_PBx_FMP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					UCPD2_STROBE rw	UCPD1_STROBE rw	BOOSTEN rw	IR_MOD rw		IR_POL rw	PA11_PA12_RMP rw			MEM_MODE rw

Toggle Fields

MEM_MODE

Bits 0-1: Memory mapping selection bits.

PA11_PA12_RMP

Bit 4: PA11 and PA12 remapping bit..

IR_POL

Bit 5: IR output polarity selection.

IR_MOD

Bits 6-7: IR Modulation Envelope signal selection..

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

UCPD1_STROBE

Bit 9: Strobe signal bit for UCPD1.

UCPD2_STROBE

Bit 10: Strobe signal bit for UCPD2.

I2C_PBx_FMP

Bits 16-19: Fast Mode Plus (FM+) driving capability activation bits.

I2C1_FMP

Bit 20: FM+ driving capability activation for I2C1.

I2C2_FMP

Bit 21: FM+ driving capability activation for I2C2.

I2C_PAx_FMP

Bits 22-23: Fast Mode Plus (FM+) driving capability activation bits.

CFGR2

SYSCFG configuration register 1

Offset: 0x18, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAM_PEF rw					ECC_LOCK rw	PVD_LOCK rw	SRAM_PARITY_LOCK rw	LOCKUP_LOCK rw

Toggle Fields

LOCKUP_LOCK

Bit 0: Cortex-M0+ LOCKUP bit enable bit.

SRAM_PARITY_LOCK

Bit 1: SRAM parity lock bit.

PVD_LOCK

Bit 2: PVD lock enable bit.

ECC_LOCK

Bit 3: ECC error lock bit.

SRAM_PEF

Bit 8: SRAM parity error flag.

VREFBUF_CSR

VREFBUF control and status register

Offset: 0x30, reset: 0x00000002, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									VRS rw			VRR r		HIZ rw	ENVR rw

Toggle Fields

ENVR

Bit 0: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode..

HIZ

Bit 1: High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration..

VRR

Bit 3: Voltage reference buffer ready.

VRS

Bits 4-6: Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved.

VREFBUF_CCR

VREFBUF calibration control register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRIM rw

Toggle Fields

TRIM

Bits 0-5: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage..

ITLINE0

interrupt line 0 status register

Offset: 0x80, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WWDG r

Toggle Fields

WWDG

Bit 0: Window watchdog interrupt pending flag.

ITLINE1

interrupt line 1 status register

Offset: 0x84, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															PVDOUT r

Toggle Fields

PVDOUT

Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16)..

ITLINE2

interrupt line 2 status register

Offset: 0x88, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RTC r	TAMP r

Toggle Fields

TAMP

Bit 0: TAMP.

RTC

Bit 1: RTC.

ITLINE3

interrupt line 3 status register

Offset: 0x8C, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														FLASH_ECC r	FLASH_ITF r

Toggle Fields

FLASH_ITF

Bit 0: FLASH_ITF.

FLASH_ECC

Bit 1: FLASH_ECC.

ITLINE4

interrupt line 4 status register

Offset: 0x90, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RCC r

Toggle Fields

RCC

Bit 0: RCC.

ITLINE5

interrupt line 5 status register

Offset: 0x94, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EXTI1 r	EXTI0 r

Toggle Fields

EXTI0

Bit 0: EXTI0.

EXTI1

Bit 1: EXTI1.

ITLINE6

interrupt line 6 status register

Offset: 0x98, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EXTI3 r	EXTI2 r

Toggle Fields

EXTI2

Bit 0: EXTI2.

EXTI3

Bit 1: EXTI3.

ITLINE7

interrupt line 7 status register

Offset: 0x9C, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				EXTI15 r	EXTI14 r	EXTI13 r	EXTI12 r	EXTI11 r	EXTI10 r	EXTI9 r	EXTI8 r	EXTI7 r	EXTI6 r	EXTI5 r	EXTI4 r

Toggle Fields

EXTI4

Bit 0: EXTI4.

EXTI5

Bit 1: EXTI5.

EXTI6

Bit 2: EXTI6.

EXTI7

Bit 3: EXTI7.

EXTI8

Bit 4: EXTI8.

EXTI9

Bit 5: EXTI9.

EXTI10

Bit 6: EXTI10.

EXTI11

Bit 7: EXTI11.

EXTI12

Bit 8: EXTI12.

EXTI13

Bit 9: EXTI13.

EXTI14

Bit 10: EXTI14.

EXTI15

Bit 11: EXTI15.

ITLINE8

interrupt line 8 status register

Offset: 0xA0, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														UCPD2 r	UCPD1 r

Toggle Fields

UCPD1

Bit 0: UCPD1.

UCPD2

Bit 1: UCPD2.

ITLINE9

interrupt line 9 status register

Offset: 0xA4, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															DMA1_CH1 r

Toggle Fields

DMA1_CH1

Bit 0: DMA1_CH1.

ITLINE10

interrupt line 10 status register

Offset: 0xA8, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														DMA1_CH3 r	DMA1_CH2 r

Toggle Fields

DMA1_CH2

Bit 0: DMA1_CH1.

DMA1_CH3

Bit 1: DMA1_CH3.

ITLINE11

interrupt line 11 status register

Offset: 0xAC, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMA1_CH7 r	DMA1_CH6 r	DMA1_CH5 r	DMA1_CH4 r	DMAMUX r

Toggle Fields

DMAMUX

Bit 0: DMAMUX.

DMA1_CH4

Bit 1: DMA1_CH4.

DMA1_CH5

Bit 2: DMA1_CH5.

DMA1_CH6

Bit 3: DMA1_CH6.

DMA1_CH7

Bit 4: DMA1_CH7.

ITLINE12

interrupt line 12 status register

Offset: 0xB0, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													COMP2 r	COMP1 r	ADC r

Toggle Fields

ADC

Bit 0: ADC.

COMP1

Bit 1: COMP1.

COMP2

Bit 2: COMP2.

ITLINE13

interrupt line 13 status register

Offset: 0xB4, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TIM1_BRK r	TIM1_UPD r	TIM1_TRG r	TIM1_CCU r

Toggle Fields

TIM1_CCU

Bit 0: TIM1_CCU.

TIM1_TRG

Bit 1: TIM1_TRG.

TIM1_UPD

Bit 2: TIM1_UPD.

TIM1_BRK

Bit 3: TIM1_BRK.

ITLINE14

interrupt line 14 status register

Offset: 0xB8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TIM1_CC r

Toggle Fields

TIM1_CC

Bit 0: TIM1_CC.

ITLINE15

interrupt line 15 status register

Offset: 0xBC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TIM2 r

Toggle Fields

TIM2

Bit 0: TIM2.

ITLINE16

interrupt line 16 status register

Offset: 0xC0, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TIM3 r

Toggle Fields

TIM3

Bit 0: TIM3.

ITLINE17

interrupt line 17 status register

Offset: 0xC4, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													LPTIM1 r	DAC r	TIM6 r

Toggle Fields

TIM6

Bit 0: TIM6.

DAC

Bit 1: DAC.

LPTIM1

Bit 2: LPTIM1.

ITLINE18

interrupt line 18 status register

Offset: 0xC8, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														LPTIM2 r	TIM7 r

Toggle Fields

TIM7

Bit 0: TIM7.

LPTIM2

Bit 1: LPTIM2.

ITLINE19

interrupt line 19 status register

Offset: 0xCC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TIM14 r

Toggle Fields

TIM14

Bit 0: TIM14.

ITLINE20

interrupt line 20 status register

Offset: 0xD0, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TIM15 r

Toggle Fields

TIM15

Bit 0: TIM15.

ITLINE21

interrupt line 21 status register

Offset: 0xD4, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TIM16 r

Toggle Fields

TIM16

Bit 0: TIM16.

ITLINE22

interrupt line 22 status register

Offset: 0xD8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TIM17 r

Toggle Fields

TIM17

Bit 0: TIM17.

ITLINE23

interrupt line 23 status register

Offset: 0xDC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															I2C1 r

Toggle Fields

I2C1

Bit 0: I2C1.

ITLINE24

interrupt line 24 status register

Offset: 0xE0, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															I2C2 r

Toggle Fields

I2C2

Bit 0: I2C2.

ITLINE25

interrupt line 25 status register

Offset: 0xE4, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															SPI1 r

Toggle Fields

SPI1

Bit 0: SPI1.

ITLINE26

interrupt line 26 status register

Offset: 0xE8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															SPI2 r

Toggle Fields

SPI2

Bit 0: SPI2.

ITLINE27

interrupt line 27 status register

Offset: 0xEC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															USART1 r

Toggle Fields

USART1

Bit 0: USART1.

ITLINE28

interrupt line 28 status register

Offset: 0xF0, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															USART2 r

Toggle Fields

USART2

Bit 0: USART2.

ITLINE29

interrupt line 29 status register

Offset: 0xF4, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													USART5 r	USART4 r	USART3 r

Toggle Fields

USART3

Bit 0: USART3.

USART4

Bit 1: USART4.

USART5

Bit 2: USART5.

ITLINE30

interrupt line 30 status register

Offset: 0xF8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															USART2 r

Toggle Fields

USART2

Bit 0: CEC.

ITLINE31

interrupt line 31 status register

Offset: 0xFC, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														AES r	RNG r

Toggle Fields

RNG

Bit 0: RNG.

AES

Bit 1: AES.

TAMP

0x4000B000: Tamper and backup registers

25/62 fields covered. Toggle Registers

Show register map

Offset	Name	31	25	24	22	21	20	19	18	17	16	15	11	7	6	4	3	2	1	0
0x0	CR1					ITAMP6E	ITAMP5E	ITAMP4E	ITAMP3E		ITAMP1E								TAMP2E	TAMP1E
0x4	CR2		TAMP2TRG	TAMP1TRG						TAMP2MSK	TAMP1MSK								TAMP2NOER	TAMP1NOER
0xC	FLTCR													TAMPPUDIS	TAMPPRCH	TAMPFLT		TAMPFREQ
0x2C	IER					ITAMP6IE	ITAMP5IE	ITAMP4IE	ITAMP3IE		ITAMP1IE								TAMP2IE	TAMP1IE
0x30	SR				ITAMP7F	ITAMP6F	ITAMP5F	ITAMP4F	ITAMP3F		ITAMP1F								TAMP2F	TAMP1F
0x34	MISR					ITAMP6MF	ITAMP5MF	ITAMP4MF	ITAMP3MF		ITAMP1MF								TAMP2MF	TAMP1MF
0x3C	SCR				CITAMP7F	CITAMP6F	CITAMP5F	CITAMP4F	CITAMP3F		CITAMP1F								CTAMP2F	CTAMP1F
0x100	BKP0R	BKP										BKP
0x104	BKP1R	BKP										BKP
0x108	BKP2R	BKP										BKP
0x10C	BKP3R	BKP										BKP
0x110	BKP4R	BKP										BKP
0x3EC	HWCFGR2												TRUST_ZONE	PTIONREG_OUT
0x3F0	HWCFGR1	INT_TAMPER										ACTIVE_TAMPER	TAMPER	BACKUP_REGS
0x3F4	VERR													MAJREV			MINREV
0x3F8	IPIDR	IPID										IPID
0x3FC	SIDR	SID										SID

CR1

control register 1

Offset: 0x0, reset: 0xFFFF0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										ITAMP6E rw	ITAMP5E rw	ITAMP4E rw	ITAMP3E rw		ITAMP1E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TAMP2E rw	TAMP1E rw

Toggle Fields

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

ITAMP1E

Bit 16: ITAMP1E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP4E

Bit 19: ITAMP4E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP6E

Bit 21: ITAMP6E.

CR2

control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TAMP2TRG rw	TAMP1TRG rw							TAMP2MSK rw	TAMP1MSK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TAMP2NOER rw	TAMP1NOER rw

Toggle Fields

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

FLTCR

TAMP filter control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMPPUDIS rw	TAMPPRCH rw		TAMPFLT rw		TAMPFREQ rw

Toggle Fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

IER

TAMP interrupt enable register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										ITAMP6IE rw	ITAMP5IE rw	ITAMP4IE rw	ITAMP3IE rw		ITAMP1IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TAMP2IE rw	TAMP1IE rw

Toggle Fields

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

ITAMP1IE

Bit 16: ITAMP1IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP4IE

Bit 19: ITAMP4IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP6IE

Bit 21: ITAMP6IE.

SR

TAMP status register

Offset: 0x30, reset: 0x00000000, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									ITAMP7F r	ITAMP6F r	ITAMP5F r	ITAMP4F r	ITAMP3F r		ITAMP1F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TAMP2F r	TAMP1F r

Toggle Fields

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

ITAMP1F

Bit 16: ITAMP1F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP4F

Bit 19: ITAMP4F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP6F

Bit 21: ITAMP6F.

ITAMP7F

Bit 22: ITAMP7F.

MISR

TAMP masked interrupt status register

Offset: 0x34, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										ITAMP6MF r	ITAMP5MF r	ITAMP4MF r	ITAMP3MF r		ITAMP1MF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TAMP2MF r	TAMP1MF r

Toggle Fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP4MF

Bit 19: ITAMP4MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP6MF

Bit 21: ITAMP6MF.

SCR

TAMP status clear register

Offset: 0x3C, reset: 0x00000000, access: write-only

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									CITAMP7F w	CITAMP6F w	CITAMP5F w	CITAMP4F w	CITAMP3F w		CITAMP1F w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CTAMP2F w	CTAMP1F w

Toggle Fields

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP4F

Bit 19: CITAMP4F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP6F

Bit 21: CITAMP6F.

CITAMP7F

Bit 22: CITAMP7F.

BKP0R

TAMP backup register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields

BKP

Bits 0-31: BKP.

BKP1R

TAMP backup register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields

BKP

Bits 0-31: BKP.

BKP2R

TAMP backup register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields

BKP

Bits 0-31: BKP.

BKP3R

TAMP backup register

Offset: 0x10C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields

BKP

Bits 0-31: BKP.

BKP4R

TAMP backup register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields

BKP

Bits 0-31: BKP.

HWCFGR2

TAMP hardware configuration register 2

Offset: 0x3EC, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TRUST_ZONE r				PTIONREG_OUT r

Toggle Fields

PTIONREG_OUT

Bits 0-7: PTIONREG_OUT.

TRUST_ZONE

Bits 8-11: TRUST_ZONE.

HWCFGR1

TAMP hardware configuration register 1

Offset: 0x3F0, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INT_TAMPER r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE_TAMPER r				TAMPER r				BACKUP_REGS r

Toggle Fields

BACKUP_REGS

Bits 0-7: BACKUP_REGS.

TAMPER

Bits 8-11: TAMPER.

ACTIVE_TAMPER

Bits 12-15: ACTIVE_TAMPER.

INT_TAMPER

Bits 16-31: INT_TAMPER.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3F8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3FC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields

SID

Bits 0-31: Size Identification.

TIM1

0x40012C00: Advanced-timers

13/195 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																				UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2									MMS2				OIS6		OIS5		OIS4	OIS3N	OIS3	OIS2N	OIS2	OIS1N	OIS1	TI1S	MMS			CCDS	CCUS		CCPC
0x8	SMCR										TS					SMS_3	ETP	ECE	ETPS		ETF				MSM	TS_4			OCCS	SMS
0xC	DIER																	TDE	COMDE	CC4DE	CC3DE	CC2DE	CC1DE	UDE	BIE	TIE	COMIE	CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR														CC6IF	CC5IF			SBIF	CC4OF	CC3OF	CC2OF	CC1OF	B2IF	BIF	TIF	COMIF	CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																							B2G	BG	TG	COMG	CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input																OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x18	CCMR1_Output								OC2M_3							OC1M_3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1C	CCMR2_Input																OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x1C	CCMR2_Output								OC4M_3							OC3M_3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER										CC6P	CC6E			CC5P	CC5E	CC4NP		CC4P	CC4E	CC3NP	CC3NE	CC3P	CC3E	CC2NP	CC2NE	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY															CNT
0x28	PSC																PSC
0x2C	ARR																ARR
0x30	RCR																REP
0x34	CCR1																CCR1
0x38	CCR2																CCR2
0x3C	CCR3																CCR3
0x40	CCR4																CCR4
0x44	BDTR			BK2ID	BKBID	BK2DSRM	BKDSRM	BK2P	BK2E	BK2F			BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR																			DBL								DBA
0x4C	DMAR																DMAB
0x50	OR1																															OCREF_CLR
0x54	CCMR3_Output								OC6M_3							OC5M_3	OC6CE	OC6M			OC6PE	OC6FE			OC5CE	OC5M			OC5PE	OC5FE
0x58	CCR5	GC5C3	GC5C2	GC5C1													CCR5
0x5C	CCR6																CCR6
0x60	AF1															ETRSEL	ETRSEL				BKCMP2P	BKCMP1P	BKINP							BKCMP2E	BKCMP1E	BKINE
0x64	AF2																				BK2CMP2P	BK2CMP1P	BK2INP	BK2DFBK0E						BK2CMP2E	BK2CMP1E	BK2INE

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								MMS2 rw					OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle Fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS5

Bit 16: Output Idle state 5 (OC5 output).

OIS6

Bit 18: Output Idle state 6 (OC6 output).

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS rw					SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_4 rw			OCCS rw	SMS rw

Toggle Fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_4

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection - bit 3.

TS

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SBIF rw	CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle Fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (output mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REP rw

Toggle Fields

REP

Bits 0-15: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle Fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle Fields

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3 rw

Toggle Fields

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4 rw

Toggle Fields

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		BK2ID rw	BKBID rw	BK2DSRM rw	BKDSRM rw	BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle Fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2ID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

option register 1

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															OCREF_CLR rw

Toggle Fields

OCREF_CLR

Bit 0: Ocref_clr source selection.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, reset: 0x00000000, access: read-write

4/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M_3 rw								OC5M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M rw			OC5PE rw	OC5FE rw

Toggle Fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_3

Bit 16: Output Compare 5 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC6M_3

Bit 24: Output Compare 6 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register 4

Offset: 0x58, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle Fields

CCR5

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 4

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle Fields

CCR6

Bits 0-15: Capture/Compare value.

AF1

DMA address for full transfer

Offset: 0x60, reset: 0x00000001, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

AF2

DMA address for full transfer

Offset: 0x64, reset: 0x00000001, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BK2CMP2P rw	BK2CMP1P rw	BK2INP rw	BK2DFBK0E rw						BK2CMP2E rw	BK2CMP1E rw	BK2INE rw

Toggle Fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TIM14

0x40002000: General purpose timers

1/32 fields covered. Toggle Registers

Show register map

Offset	Name	31	16	15	11	9	7	6	3	2	1	0
0x0	CR1				UIFREMAP	CKD	ARPE		OPM	URS	UDIS	CEN
0xC	DIER										CC1IE	UIE
0x10	SR					CC1OF					CC1IF	UIF
0x14	EGR										CC1G	UG
0x18	CCMR1_Input						IC1F		ICPCS		CC1S
0x18	CCMR1_Output		OC1M_3				OC1CE	OC1M	OC1PE	OC1FE	CC1S
0x20	CCER								CC1NP		CC1P	CC1E
0x24	CNT	UIFCPY		CNT
0x28	PSC			PSC
0x2C	ARR			ARR
0x34	CCR1			CCR1
0x68	TISEL								TISEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC1IE rw	UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw								CC1IF rw	UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC1G w	UG w

Toggle Fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				ICPCS rw		CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields

CC1S

Bits 0-1: CC1S.

OC1FE

Bit 2: OC1FE.

OC1PE

Bit 3: OC1PE.

OC1M

Bits 4-6: OC1M.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1CE

Bit 7: OC1CE.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw		CC1P rw	CC1E rw

Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields

CNT

Bits 0-15: low counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Low Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

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15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle Fields

CCR1

Bits 0-15: Low Capture/Compare 1 value.

TISEL

TIM timer input selection register

Offset: 0x68, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TISEL rw

Toggle Fields

TISEL

Bits 0-3: TI1[0] to TI1[15] input selection.

TIM15

0x40014000: General purpose timers

67/89 fields covered. Toggle Registers

Show register map

Offset	Name	31	28	26	24	21	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1												UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2													OIS2	OIS1N	OIS1	TI1S	MMS			CCDS	CCUS		CCPC
0x8	SMCR					TS2		SMS2									MSM	TS1				SMS1
0xC	DIER									TDE	COMDE			CC2DE	CC1DE	UDE	BIE	TIE	COMIE			CC2IE	CC1IE	UIE
0x10	SR													CC2OF	CC1OF		BIF	TIF	COMIF			CC2IF	CC1IF	UIF
0x14	EGR																BG	TG	COMG			CC2G	CC1G	UG
0x18	CCMR1_Input								IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output				OC2M_3			OC1M_3		OC2M			OC2PE	OC2FE	CC2S			OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																CC2NP		CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY							CNT
0x28	PSC								PSC
0x2C	ARR								ARR
0x30	RCR																REP
0x34	CCR1								CCR1
0x38	CCR2								CCR2
0x44	BDTR		BKBID	BKDSRM			BKF		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR											DBL								DBA
0x4C	DMAR								DMAB

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt if enabled

OPM

Bit 3: One-pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the bit CEN)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered
0x1: B_0x1: TIMx_ARR register is buffered

CKD

Bits 8-9: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx).

Allowed values:
0x0: B_0x0: tDTS = tCK_INT
0x1: B_0x1: tDTS = 2*tCK_INT
0x2: B_0x2: tDTS = 4*tCK_INT
0x3: B_0x3: Reserved, do not program this value

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

8/8 fields covered.

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15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle Fields

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0x0: B_0x0: CCx DMA request sent when CCx event occurs
0x1: B_0x1: CCx DMA requests sent when update event occurs

MMS

Bits 4-6: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:.

Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO).
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO).

TI1S

Bit 7: TI1 selection.

Allowed values:
0x0: B_0x0: The TIMx_CH1 pin is connected to TI1 input
0x1: B_0x1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination)

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..

Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..

Allowed values:
0x0: B_0x0: OC1N=0 after a dead-time when MOE=0
0x1: B_0x1: OC1N=1 after a dead-time when MOE=0

OIS2

Bit 10: Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register)..

Allowed values:
0x0: B_0x0: OC2=0 when MOE=0
0x1: B_0x1: OC2=1 when MOE=0

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS2 rw					SMS2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MSM rw	TS1 rw				SMS1 rw

Toggle Fields

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS1

Bits 4-6: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/slave mode.

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

11/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw			CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw			CC2IE rw	CC1IE rw	UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled
0x1: B_0x1: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0x0: B_0x0: CC1 interrupt disabled
0x1: B_0x1: CC1 interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0x0: B_0x0: CC2 interrupt disabled
0x1: B_0x1: CC2 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0x0: B_0x0: COM interrupt disabled
0x1: B_0x1: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0x0: B_0x0: Trigger interrupt disabled
0x1: B_0x1: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0x0: B_0x0: Break interrupt disabled
0x1: B_0x1: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled
0x1: B_0x1: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0x0: B_0x0: CC1 DMA request disabled
0x1: B_0x1: CC1 DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0x0: B_0x0: CC2 DMA request disabled
0x1: B_0x1: CC2 DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0x0: B_0x0: COM DMA request disabled
0x1: B_0x1: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0x0: B_0x0: Trigger DMA request disabled
0x1: B_0x1: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

6/8 fields covered.

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15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CC2OF rw	CC1OF rw		BIF rw	TIF rw	COMIF rw			CC2IF rw	CC1IF rw	UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred

CC2IF

Bit 2: Capture/Compare 2 interrupt flag refer to CC1IF description.

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits âCCxE, CCxNE, OCxMâ have been updated). It is cleared by software..

Allowed values:
0x0: B_0x0: No COM event occurred
0x1: B_0x1: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

Allowed values:
0x0: B_0x0: No trigger event occurred
0x1: B_0x1: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

Allowed values:
0x0: B_0x0: No break event occurred
0x1: B_0x1: An active level has been detected on the break input

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..

Allowed values:
0x0: B_0x0: No overcapture has been detected
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

CC2OF

Bit 10: Capture/Compare 2 overcapture flag Refer to CC1OF description.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

5/6 fields covered.

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15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG rw			CC2G w	CC1G w	UG w

Toggle Fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:

CC2G

Bit 2: Capture/Compare 2 generation Refer to CC1G description.

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

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15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register)..

Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC2 channel is configured as output
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

8/10 fields covered.

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							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw			OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC1 channel is configured as output.
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1.
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2.
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

OC1FE

Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

Allowed values:
0x0: B_0x0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x1: B_0x1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

OC1PE

Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

OC1M

Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16..

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

CC2S

Allowed values:
0x0: B_0x0: CC2 channel is configured as output.
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2.
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1.
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC1M_3

Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16..

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

4/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CC2NP rw		CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: OC1N active high
0x1: B_0x1: OC1N active low

CC2E

Bit 4: Capture/Compare 2 output enable Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output polarity Refer to CC1P description.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity Refer to CC1NP description.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle Fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle Fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle Fields

CCR2

Bits 0-15: Capture/Compare 2 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

10/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw							BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle Fields

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 Âµs to 31750 ns by 250 ns steps, 32 Âµs to 63 Âµs by 1 Âµs steps, 64 Âµs to 126 Âµs by 2 Âµs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on pageÂ 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x1: B_0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on pageÂ 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break inputs (BRK and CCS clock failure event) disabled

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if the break input is not be active)

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on pageÂ 818)..

Allowed values:
0x0: B_0x0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....

Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....

Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM16

0x40014400: General purpose timers

2/69 fields covered. Toggle Registers

Show register map

Offset	Name	31	28	26	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1										UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2												OIS1N	OIS1					CCDS	CCUS		CCPC
0xC	DIER								COMDE				CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10	SR												CC1OF		BIF		COMIF				CC1IF	UIF
0x14	EGR														BG		COMG				CC1G	UG
0x18	CCMR1_Input														IC1F				IC1PSC		CC1S
0x18	CCMR1_Output					OC1M_2										OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																		CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY					CNT
0x28	PSC						PSC
0x2C	ARR						ARR
0x30	RCR														REP
0x34	CCR1						CCR1
0x44	BDTR		BKBID	BKDSRM	BKF		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR									DBL								DBA
0x4C	DMAR						DMAB
0x60	AF1										BKCMP2P	BKCMP1P	BKINP	BKDFBK1E						BKCMP2E	BKCMP1E	BKINE
0x68	TISEL										TI2SEL								TI1SEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle Fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		COMDE rw				CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle Fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle Fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle Fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw							BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle Fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM17 option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw	BKDFBK1E rw						BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK1E

Bit 8: BRK DFSDM_BREAK1 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TISEL

input selection register

Offset: 0x68, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle Fields

TI1SEL

Bits 0-3: selects input.

TI2SEL

Bits 8-11: selects input.

TIM17

0x40014800: General purpose timers

2/69 fields covered. Toggle Registers

Show register map

Offset	Name	31	28	26	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1										UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2												OIS1N	OIS1					CCDS	CCUS		CCPC
0xC	DIER								COMDE				CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10	SR												CC1OF		BIF		COMIF				CC1IF	UIF
0x14	EGR														BG		COMG				CC1G	UG
0x18	CCMR1_Input														IC1F				IC1PSC		CC1S
0x18	CCMR1_Output					OC1M_2										OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																		CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY					CNT
0x28	PSC						PSC
0x2C	ARR						ARR
0x30	RCR														REP
0x34	CCR1						CCR1
0x44	BDTR		BKBID	BKDSRM	BKF		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR									DBL								DBA
0x4C	DMAR						DMAB
0x60	AF1										BKCMP2P	BKCMP1P	BKINP	BKDFBK1E						BKCMP2E	BKCMP1E	BKINE
0x68	TISEL										TI2SEL								TI1SEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle Fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		COMDE rw				CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle Fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle Fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle Fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw							BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle Fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM17 option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw	BKDFBK1E rw						BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK1E

Bit 8: BRK DFSDM_BREAK1 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TISEL

input selection register

Offset: 0x68, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle Fields

TI1SEL

Bits 0-3: selects input.

TI2SEL

Bits 8-11: selects input.

TIM2

0x40000000: General-purpose-timers

8/118 fields covered. Toggle Registers

Show register map

Offset	Name	31	24	21	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1										UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2														TI1S	MMS			CCDS
0x8	SMCR			TS_4_3		SMS_3	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xC	DIER							TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR									CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR															TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input						IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output		OC2M_3			OC1M_3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1C	CCMR2_Input						IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1C	CCMR2_Output		OC4M_3			OC3M_3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER						CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_H					CNT_L
0x28	PSC						PSC
0x2C	ARR	ARR_H					ARR_L
0x34	CCR1	CCR1_H					CCR1_L
0x38	CCR2	CCR2_H					CCR2_L
0x3C	CCR3	CCR3_H					CCR3_L
0x40	CCR4	CCR4_H					CCR4_L
0x48	DCR									DBL								DBA
0x4C	DMAR						DMAB
0x50	OR1																					IOCREF_CLR
0x60	AF1				ETRSEL		ETRSEL
0x68	TISEL										TI2SEL								TI1SEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle Fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS_4_3 rw					SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle Fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle Fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle Fields

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-31: High counter value (TIM2 only).

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle Fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle Fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle Fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle Fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle Fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM option register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															IOCREF_CLR rw

Toggle Fields

IOCREF_CLR

Bit 0: IOCREF_CLR.

AF1

TIM alternate function option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle Fields

ETRSEL

Bits 14-17: External trigger source selection.

TISEL

TIM alternate function option register 1

Offset: 0x68, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle Fields

TI1SEL

Bits 0-3: TI1SEL.

TI2SEL

Bits 8-11: TI2SEL.

TIM3

0x40000400: General-purpose-timers

8/118 fields covered. Toggle Registers

Show register map

Offset	Name	31	24	21	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1										UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2														TI1S	MMS			CCDS
0x8	SMCR			TS_4_3		SMS_3	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xC	DIER							TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR									CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR															TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input						IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output		OC2M_3			OC1M_3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1C	CCMR2_Input						IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1C	CCMR2_Output		OC4M_3			OC3M_3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER						CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_H					CNT_L
0x28	PSC						PSC
0x2C	ARR	ARR_H					ARR_L
0x34	CCR1	CCR1_H					CCR1_L
0x38	CCR2	CCR2_H					CCR2_L
0x3C	CCR3	CCR3_H					CCR3_L
0x40	CCR4	CCR4_H					CCR4_L
0x48	DCR									DBL								DBA
0x4C	DMAR						DMAB
0x50	OR1																					IOCREF_CLR
0x60	AF1				ETRSEL		ETRSEL
0x68	TISEL										TI2SEL								TI1SEL

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle Fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS_4_3 rw					SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle Fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle Fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle Fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle Fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle Fields

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-31: High counter value (TIM2 only).

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle Fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle Fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle Fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle Fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle Fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM option register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															IOCREF_CLR rw

Toggle Fields

IOCREF_CLR

Bit 0: IOCREF_CLR.

AF1

TIM alternate function option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle Fields

ETRSEL

Bits 14-17: External trigger source selection.

TISEL

TIM alternate function option register 1

Offset: 0x68, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle Fields

TI1SEL

Bits 0-3: TI1SEL.

TI2SEL

Bits 8-11: TI2SEL.

TIM6

0x40001000: Basic timers

0/15 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	8	7	6	3	2	1	0
0x0	CR1			UIFREMAP		ARPE		OPM	URS	UDIS	CEN
0x4	CR2						MMS
0xC	DIER				UDE						UIE
0x10	SR										UIF
0x14	EGR										UG
0x24	CNT	UIFCPY	CNT
0x28	PSC		PSC
0x2C	ARR		ARR

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw				ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle Fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							UDE rw								UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

UDE

Bit 8: Update DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															UG w

Toggle Fields

UG

Bit 0: Update generation.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields

CNT

Bits 0-15: Low counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Low Auto-reload value.

TIM7

0x40001400: Basic timers

0/15 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	8	7	6	3	2	1	0
0x0	CR1			UIFREMAP		ARPE		OPM	URS	UDIS	CEN
0x4	CR2						MMS
0xC	DIER				UDE						UIE
0x10	SR										UIF
0x14	EGR										UG
0x24	CNT	UIFCPY	CNT
0x28	PSC		PSC
0x2C	ARR		ARR

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw				ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle Fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							UDE rw								UIE rw

Toggle Fields

UIE

Bit 0: Update interrupt enable.

UDE

Bit 8: Update DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															UIF rw

Toggle Fields

UIF

Bit 0: Update interrupt flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															UG w

Toggle Fields

UG

Bit 0: Update generation.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields

CNT

Bits 0-15: Low counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields

ARR

Bits 0-15: Low Auto-reload value.

UCPD1

0x4000A000: USB Power Delivery interface

25/92 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	24	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CFG1	UCPDEN	RXDMAEN	TXDMAEN	RXORDSETEN				PSC_USBPDCLK				TRANSWIN					IFRGAP					HBITCLKDIV
0x4	CFG2																								WUPEN	FORCECLK	RXFILT2N3	RXFILTDIS
0x8	CFG3				TRIM2_NG_CC3A0	TRIM2_NG_CC1A5			TRIM2_NG_CCRPD							TRIM1_NG_CC3A0				TRIM1_NG_CC1A5					TRIM1_NG_CCRPD
0xC	CR						CC2TCDIS	CC1TCDIS		RDCH	FRSTX	FRSRXEN	DBATTEN				CCENABLE		ANAMODE	ANASUBMODE		PHYCCSEL	PHYRXEN	RXMODE	TXHRST	TXSEND	TXMODE
0x10	IMR							FRSEVTIE					TYPECEVT2IE	TYPECEVT1IE		RXMSGENDIE	RXOVRIE	RXHRSTDETIE	RXORDDETIE	RXNEIE		TXUNDIE	HRSTSENTIE	HRSTDISCIE	TXMSGABTIE	TXMSGSENTIE	TXMSGDISCIE	TXISIE
0x14	SR							FRSEVT	TYPEC_VSTATE_CC2		TYPEC_VSTATE_CC1		TYPECEVT2	TYPECEVT1	RXERR	RXMSGEND	RXOVR	RXHRSTDET	RXORDDET	RXNE		TXUND	HRSTSENT	HRSTDISC	TXMSGABT	TXMSGSENT	TXMSGDISC	TXIS
0x18	ICR							FRSEVTCF					TYPECEVT2CF	TYPECEVT1CF		RXMSGENDCF	RXOVRCF	RXHRSTDETCF	RXORDDETCF			TXUNDCF	HRSTSENTCF	HRSTDISCCF	TXMSGABTCF	TXMSGSENTCF	TXMSGDISCCF
0x1C	TX_ORDSET								TXORDSET				TXORDSET
0x20	TX_PAYSZ																		TXPAYSZ
0x24	TXDR																				TXDATA
0x28	RX_ORDSET																					RXSOPKINVALID			RXSOP3OF4	RXORDSET
0x2C	RX_PAYSZ																		RXPAYSZ
0x30	RXDR																				RXDATA
0x34	RX_ORDEXT1								RXSOPX1				RXSOPX1
0x38	RX_ORDEXT2								RXSOPX2				RXSOPX2
0x3F4	IPVER	IPVER											IPVER
0x3F8	IPID	IPID											IPID
0x3FC	MID	IPID											IPID

CFG1

UCPD configuration register

Offset: 0x0, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UCPDEN rw	RXDMAEN rw	TXDMAEN rw	RXORDSETEN rw									PSC_USBPDCLK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRANSWIN rw					IFRGAP rw					HBITCLKDIV rw

Toggle Fields

HBITCLKDIV

Bits 0-5: HBITCLKDIV.

IFRGAP

Bits 6-10: IFRGAP.

TRANSWIN

Bits 11-15: TRANSWIN.

PSC_USBPDCLK

Bits 17-19: PSC_USBPDCLK.

RXORDSETEN

Bits 20-28: RXORDSETEN.

TXDMAEN

Bit 29: TXDMAEN.

RXDMAEN

Bit 30: RXDMAEN:.

UCPDEN

Bit 31: UCPDEN.

CFG2

UCPD configuration register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												WUPEN rw	FORCECLK rw	RXFILT2N3 rw	RXFILTDIS rw

Toggle Fields

RXFILTDIS

Bit 0: RXFILTDIS.

RXFILT2N3

Bit 1: RXFILT2N3.

FORCECLK

Bit 2: FORCECLK.

WUPEN

Bit 3: WUPEN.

CFG3

UCPD configuration register 3

Offset: 0x8, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			TRIM2_NG_CC3A0 rw				TRIM2_NG_CC1A5 rw					TRIM2_NG_CCRPD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIM1_NG_CC3A0 rw				TRIM1_NG_CC1A5 rw					TRIM1_NG_CCRPD rw

Toggle Fields

TRIM1_NG_CCRPD

Bits 0-3: TRIM1_NG_CCRPD.

TRIM1_NG_CC1A5

Bits 4-8: TRIM1_NG_CC1A5.

TRIM1_NG_CC3A0

Bits 9-12: TRIM1_NG_CC3A0.

TRIM2_NG_CCRPD

Bits 16-19: TRIM2_NG_CCRPD.

TRIM2_NG_CC1A5

Bits 20-24: TRIM2_NG_CC1A5.

TRIM2_NG_CC3A0

Bits 25-28: TRIM2_NG_CC3A0.

CR

UCPD control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC2TCDIS rw	CC1TCDIS rw		RDCH rw	FRSTX rw	FRSRXEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBATTEN rw				CCENABLE rw		ANAMODE rw	ANASUBMODE rw		PHYCCSEL rw	PHYRXEN rw	RXMODE rw	TXHRST rw	TXSEND rw	TXMODE rw

Toggle Fields

TXMODE

Bits 0-1: TXMODE.

TXSEND

Bit 2: TXSEND.

TXHRST

Bit 3: TXHRST.

RXMODE

Bit 4: RXMODE.

PHYRXEN

Bit 5: PHYRXEN.

PHYCCSEL

Bit 6: PHYCCSEL.

ANASUBMODE

Bits 7-8: ANASUBMODE.

ANAMODE

Bit 9: ANAMODE.

CCENABLE

Bits 10-11: CCENABLE.

DBATTEN

Bit 15: DBATTEN.

FRSRXEN

Bit 16: FRSRXEN.

FRSTX

Bit 17: FRSTX.

RDCH

Bit 18: RDCH.

CC1TCDIS

Bit 20: CC1TCDIS.

CC2TCDIS

Bit 21: CC2TCDIS.

IMR

UCPD Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											FRSEVTIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TYPECEVT2IE rw	TYPECEVT1IE rw		RXMSGENDIE rw	RXOVRIE rw	RXHRSTDETIE rw	RXORDDETIE rw	RXNEIE rw		TXUNDIE rw	HRSTSENTIE rw	HRSTDISCIE rw	TXMSGABTIE rw	TXMSGSENTIE rw	TXMSGDISCIE rw	TXISIE rw

Toggle Fields

TXISIE

Bit 0: TXISIE.

TXMSGDISCIE

Bit 1: TXMSGDISCIE.

TXMSGSENTIE

Bit 2: TXMSGSENTIE.

TXMSGABTIE

Bit 3: TXMSGABTIE.

HRSTDISCIE

Bit 4: HRSTDISCIE.

HRSTSENTIE

Bit 5: HRSTSENTIE.

TXUNDIE

Bit 6: TXUNDIE.

RXNEIE

Bit 8: RXNEIE.

RXORDDETIE

Bit 9: RXORDDETIE.

RXHRSTDETIE

Bit 10: RXHRSTDETIE.

RXOVRIE

Bit 11: RXOVRIE.

RXMSGENDIE

Bit 12: RXMSGENDIE.

TYPECEVT1IE

Bit 14: TYPECEVT1IE.

TYPECEVT2IE

Bit 15: TYPECEVT2IE.

FRSEVTIE

Bit 20: FRSEVTIE.

SR

UCPD Status Register

Offset: 0x14, reset: 0x00000000, access: read-only

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											FRSEVT r	TYPEC_VSTATE_CC2 r		TYPEC_VSTATE_CC1 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TYPECEVT2 r	TYPECEVT1 r	RXERR r	RXMSGEND r	RXOVR r	RXHRSTDET r	RXORDDET r	RXNE r		TXUND r	HRSTSENT r	HRSTDISC r	TXMSGABT r	TXMSGSENT r	TXMSGDISC r	TXIS r

Toggle Fields

TXIS

Bit 0: TXIS.

TXMSGDISC

Bit 1: TXMSGDISC.

TXMSGSENT

Bit 2: TXMSGSENT.

TXMSGABT

Bit 3: TXMSGABT.

HRSTDISC

Bit 4: HRSTDISC.

HRSTSENT

Bit 5: HRSTSENT.

TXUND

Bit 6: TXUND.

RXNE

Bit 8: RXNE.

RXORDDET

Bit 9: RXORDDET.

RXHRSTDET

Bit 10: RXHRSTDET.

RXOVR

Bit 11: RXOVR.

RXMSGEND

Bit 12: RXMSGEND.

RXERR

Bit 13: RXERR.

TYPECEVT1

Bit 14: TYPECEVT1.

TYPECEVT2

Bit 15: TYPECEVT2.

TYPEC_VSTATE_CC1

Bits 16-17: TYPEC_VSTATE_CC1.

TYPEC_VSTATE_CC2

Bits 18-19: TYPEC_VSTATE_CC2.

FRSEVT

Bit 20: FRSEVT.

ICR

UCPD Interrupt Clear Register

Offset: 0x18, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											FRSEVTCF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TYPECEVT2CF rw	TYPECEVT1CF rw		RXMSGENDCF rw	RXOVRCF rw	RXHRSTDETCF rw	RXORDDETCF rw			TXUNDCF rw	HRSTSENTCF rw	HRSTDISCCF rw	TXMSGABTCF rw	TXMSGSENTCF rw	TXMSGDISCCF rw

Toggle Fields

TXMSGDISCCF

Bit 1: TXMSGDISCCF.

TXMSGSENTCF

Bit 2: TXMSGSENTCF.

TXMSGABTCF

Bit 3: TXMSGABTCF.

HRSTDISCCF

Bit 4: HRSTDISCCF.

HRSTSENTCF

Bit 5: HRSTSENTCF.

TXUNDCF

Bit 6: TXUNDCF.

RXORDDETCF

Bit 9: RXORDDETCF.

RXHRSTDETCF

Bit 10: RXHRSTDETCF.

RXOVRCF

Bit 11: RXOVRCF.

RXMSGENDCF

Bit 12: RXMSGENDCF.

TYPECEVT1CF

Bit 14: TYPECEVT1CF.

TYPECEVT2CF

Bit 15: TYPECEVT2CF.

FRSEVTCF

Bit 20: FRSEVTCF.

TX_ORDSET

UCPD Tx Ordered Set Type Register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												TXORDSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXORDSET rw

Toggle Fields

TXORDSET

Bits 0-19: TXORDSET.

TX_PAYSZ

UCPD Tx Paysize Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TXPAYSZ rw

Toggle Fields

TXPAYSZ

Bits 0-9: TXPAYSZ.

TXDR

UCPD Tx Data Register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle Fields

TXDATA

Bits 0-7: TXDATA.

RX_ORDSET

UCPD Rx Ordered Set Register

Offset: 0x28, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									RXSOPKINVALID r			RXSOP3OF4 r	RXORDSET r

Toggle Fields

RXORDSET

Bits 0-2: RXORDSET.

RXSOP3OF4

Bit 3: RXSOP3OF4.

RXSOPKINVALID

Bits 4-6: RXSOPKINVALID.

RX_PAYSZ

UCPD Rx Paysize Register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						RXPAYSZ rw

Toggle Fields

RXPAYSZ

Bits 0-9: RXPAYSZ.

RXDR

UCPD Receive Data Register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle Fields

RXDATA

Bits 0-7: RXDATA.

RX_ORDEXT1

UCPD Rx Ordered Set Extension Register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												RXSOPX1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXSOPX1 rw

Toggle Fields

RXSOPX1

Bits 0-19: RXSOPX1.

RX_ORDEXT2

UCPD Rx Ordered Set Extension Register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												RXSOPX2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXSOPX2 rw

Toggle Fields

RXSOPX2

Bits 0-19: RXSOPX2.

IPVER

UCPD IP ID register

Offset: 0x3F4, reset: 0x00000010, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPVER r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPVER r

Toggle Fields

IPVER

Bits 0-31: IPVER.

IPID

UCPD IP ID register

Offset: 0x3F8, reset: 0x00150021, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IPID.

MID

UCPD IP ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IPID.

UCPD2

0x4000A400: USB Power Delivery interface

25/92 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	24	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CFG1	UCPDEN	RXDMAEN	TXDMAEN	RXORDSETEN				PSC_USBPDCLK				TRANSWIN					IFRGAP					HBITCLKDIV
0x4	CFG2																								WUPEN	FORCECLK	RXFILT2N3	RXFILTDIS
0x8	CFG3				TRIM2_NG_CC3A0	TRIM2_NG_CC1A5			TRIM2_NG_CCRPD							TRIM1_NG_CC3A0				TRIM1_NG_CC1A5					TRIM1_NG_CCRPD
0xC	CR						CC2TCDIS	CC1TCDIS		RDCH	FRSTX	FRSRXEN	DBATTEN				CCENABLE		ANAMODE	ANASUBMODE		PHYCCSEL	PHYRXEN	RXMODE	TXHRST	TXSEND	TXMODE
0x10	IMR							FRSEVTIE					TYPECEVT2IE	TYPECEVT1IE		RXMSGENDIE	RXOVRIE	RXHRSTDETIE	RXORDDETIE	RXNEIE		TXUNDIE	HRSTSENTIE	HRSTDISCIE	TXMSGABTIE	TXMSGSENTIE	TXMSGDISCIE	TXISIE
0x14	SR							FRSEVT	TYPEC_VSTATE_CC2		TYPEC_VSTATE_CC1		TYPECEVT2	TYPECEVT1	RXERR	RXMSGEND	RXOVR	RXHRSTDET	RXORDDET	RXNE		TXUND	HRSTSENT	HRSTDISC	TXMSGABT	TXMSGSENT	TXMSGDISC	TXIS
0x18	ICR							FRSEVTCF					TYPECEVT2CF	TYPECEVT1CF		RXMSGENDCF	RXOVRCF	RXHRSTDETCF	RXORDDETCF			TXUNDCF	HRSTSENTCF	HRSTDISCCF	TXMSGABTCF	TXMSGSENTCF	TXMSGDISCCF
0x1C	TX_ORDSET								TXORDSET				TXORDSET
0x20	TX_PAYSZ																		TXPAYSZ
0x24	TXDR																				TXDATA
0x28	RX_ORDSET																					RXSOPKINVALID			RXSOP3OF4	RXORDSET
0x2C	RX_PAYSZ																		RXPAYSZ
0x30	RXDR																				RXDATA
0x34	RX_ORDEXT1								RXSOPX1				RXSOPX1
0x38	RX_ORDEXT2								RXSOPX2				RXSOPX2
0x3F4	IPVER	IPVER											IPVER
0x3F8	IPID	IPID											IPID
0x3FC	MID	IPID											IPID

CFG1

UCPD configuration register

Offset: 0x0, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UCPDEN rw	RXDMAEN rw	TXDMAEN rw	RXORDSETEN rw									PSC_USBPDCLK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRANSWIN rw					IFRGAP rw					HBITCLKDIV rw

Toggle Fields

HBITCLKDIV

Bits 0-5: HBITCLKDIV.

IFRGAP

Bits 6-10: IFRGAP.

TRANSWIN

Bits 11-15: TRANSWIN.

PSC_USBPDCLK

Bits 17-19: PSC_USBPDCLK.

RXORDSETEN

Bits 20-28: RXORDSETEN.

TXDMAEN

Bit 29: TXDMAEN.

RXDMAEN

Bit 30: RXDMAEN:.

UCPDEN

Bit 31: UCPDEN.

CFG2

UCPD configuration register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												WUPEN rw	FORCECLK rw	RXFILT2N3 rw	RXFILTDIS rw

Toggle Fields

RXFILTDIS

Bit 0: RXFILTDIS.

RXFILT2N3

Bit 1: RXFILT2N3.

FORCECLK

Bit 2: FORCECLK.

WUPEN

Bit 3: WUPEN.

CFG3

UCPD configuration register 3

Offset: 0x8, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			TRIM2_NG_CC3A0 rw				TRIM2_NG_CC1A5 rw					TRIM2_NG_CCRPD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIM1_NG_CC3A0 rw				TRIM1_NG_CC1A5 rw					TRIM1_NG_CCRPD rw

Toggle Fields

TRIM1_NG_CCRPD

Bits 0-3: TRIM1_NG_CCRPD.

TRIM1_NG_CC1A5

Bits 4-8: TRIM1_NG_CC1A5.

TRIM1_NG_CC3A0

Bits 9-12: TRIM1_NG_CC3A0.

TRIM2_NG_CCRPD

Bits 16-19: TRIM2_NG_CCRPD.

TRIM2_NG_CC1A5

Bits 20-24: TRIM2_NG_CC1A5.

TRIM2_NG_CC3A0

Bits 25-28: TRIM2_NG_CC3A0.

CR

UCPD control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC2TCDIS rw	CC1TCDIS rw		RDCH rw	FRSTX rw	FRSRXEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBATTEN rw				CCENABLE rw		ANAMODE rw	ANASUBMODE rw		PHYCCSEL rw	PHYRXEN rw	RXMODE rw	TXHRST rw	TXSEND rw	TXMODE rw

Toggle Fields

TXMODE

Bits 0-1: TXMODE.

TXSEND

Bit 2: TXSEND.

TXHRST

Bit 3: TXHRST.

RXMODE

Bit 4: RXMODE.

PHYRXEN

Bit 5: PHYRXEN.

PHYCCSEL

Bit 6: PHYCCSEL.

ANASUBMODE

Bits 7-8: ANASUBMODE.

ANAMODE

Bit 9: ANAMODE.

CCENABLE

Bits 10-11: CCENABLE.

DBATTEN

Bit 15: DBATTEN.

FRSRXEN

Bit 16: FRSRXEN.

FRSTX

Bit 17: FRSTX.

RDCH

Bit 18: RDCH.

CC1TCDIS

Bit 20: CC1TCDIS.

CC2TCDIS

Bit 21: CC2TCDIS.

IMR

UCPD Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											FRSEVTIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TYPECEVT2IE rw	TYPECEVT1IE rw		RXMSGENDIE rw	RXOVRIE rw	RXHRSTDETIE rw	RXORDDETIE rw	RXNEIE rw		TXUNDIE rw	HRSTSENTIE rw	HRSTDISCIE rw	TXMSGABTIE rw	TXMSGSENTIE rw	TXMSGDISCIE rw	TXISIE rw

Toggle Fields

TXISIE

Bit 0: TXISIE.

TXMSGDISCIE

Bit 1: TXMSGDISCIE.

TXMSGSENTIE

Bit 2: TXMSGSENTIE.

TXMSGABTIE

Bit 3: TXMSGABTIE.

HRSTDISCIE

Bit 4: HRSTDISCIE.

HRSTSENTIE

Bit 5: HRSTSENTIE.

TXUNDIE

Bit 6: TXUNDIE.

RXNEIE

Bit 8: RXNEIE.

RXORDDETIE

Bit 9: RXORDDETIE.

RXHRSTDETIE

Bit 10: RXHRSTDETIE.

RXOVRIE

Bit 11: RXOVRIE.

RXMSGENDIE

Bit 12: RXMSGENDIE.

TYPECEVT1IE

Bit 14: TYPECEVT1IE.

TYPECEVT2IE

Bit 15: TYPECEVT2IE.

FRSEVTIE

Bit 20: FRSEVTIE.

SR

UCPD Status Register

Offset: 0x14, reset: 0x00000000, access: read-only

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											FRSEVT r	TYPEC_VSTATE_CC2 r		TYPEC_VSTATE_CC1 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TYPECEVT2 r	TYPECEVT1 r	RXERR r	RXMSGEND r	RXOVR r	RXHRSTDET r	RXORDDET r	RXNE r		TXUND r	HRSTSENT r	HRSTDISC r	TXMSGABT r	TXMSGSENT r	TXMSGDISC r	TXIS r

Toggle Fields

TXIS

Bit 0: TXIS.

TXMSGDISC

Bit 1: TXMSGDISC.

TXMSGSENT

Bit 2: TXMSGSENT.

TXMSGABT

Bit 3: TXMSGABT.

HRSTDISC

Bit 4: HRSTDISC.

HRSTSENT

Bit 5: HRSTSENT.

TXUND

Bit 6: TXUND.

RXNE

Bit 8: RXNE.

RXORDDET

Bit 9: RXORDDET.

RXHRSTDET

Bit 10: RXHRSTDET.

RXOVR

Bit 11: RXOVR.

RXMSGEND

Bit 12: RXMSGEND.

RXERR

Bit 13: RXERR.

TYPECEVT1

Bit 14: TYPECEVT1.

TYPECEVT2

Bit 15: TYPECEVT2.

TYPEC_VSTATE_CC1

Bits 16-17: TYPEC_VSTATE_CC1.

TYPEC_VSTATE_CC2

Bits 18-19: TYPEC_VSTATE_CC2.

FRSEVT

Bit 20: FRSEVT.

ICR

UCPD Interrupt Clear Register

Offset: 0x18, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											FRSEVTCF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TYPECEVT2CF rw	TYPECEVT1CF rw		RXMSGENDCF rw	RXOVRCF rw	RXHRSTDETCF rw	RXORDDETCF rw			TXUNDCF rw	HRSTSENTCF rw	HRSTDISCCF rw	TXMSGABTCF rw	TXMSGSENTCF rw	TXMSGDISCCF rw

Toggle Fields

TXMSGDISCCF

Bit 1: TXMSGDISCCF.

TXMSGSENTCF

Bit 2: TXMSGSENTCF.

TXMSGABTCF

Bit 3: TXMSGABTCF.

HRSTDISCCF

Bit 4: HRSTDISCCF.

HRSTSENTCF

Bit 5: HRSTSENTCF.

TXUNDCF

Bit 6: TXUNDCF.

RXORDDETCF

Bit 9: RXORDDETCF.

RXHRSTDETCF

Bit 10: RXHRSTDETCF.

RXOVRCF

Bit 11: RXOVRCF.

RXMSGENDCF

Bit 12: RXMSGENDCF.

TYPECEVT1CF

Bit 14: TYPECEVT1CF.

TYPECEVT2CF

Bit 15: TYPECEVT2CF.

FRSEVTCF

Bit 20: FRSEVTCF.

TX_ORDSET

UCPD Tx Ordered Set Type Register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												TXORDSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXORDSET rw

Toggle Fields

TXORDSET

Bits 0-19: TXORDSET.

TX_PAYSZ

UCPD Tx Paysize Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TXPAYSZ rw

Toggle Fields

TXPAYSZ

Bits 0-9: TXPAYSZ.

TXDR

UCPD Tx Data Register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle Fields

TXDATA

Bits 0-7: TXDATA.

RX_ORDSET

UCPD Rx Ordered Set Register

Offset: 0x28, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									RXSOPKINVALID r			RXSOP3OF4 r	RXORDSET r

Toggle Fields

RXORDSET

Bits 0-2: RXORDSET.

RXSOP3OF4

Bit 3: RXSOP3OF4.

RXSOPKINVALID

Bits 4-6: RXSOPKINVALID.

RX_PAYSZ

UCPD Rx Paysize Register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						RXPAYSZ rw

Toggle Fields

RXPAYSZ

Bits 0-9: RXPAYSZ.

RXDR

UCPD Receive Data Register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle Fields

RXDATA

Bits 0-7: RXDATA.

RX_ORDEXT1

UCPD Rx Ordered Set Extension Register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												RXSOPX1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXSOPX1 rw

Toggle Fields

RXSOPX1

Bits 0-19: RXSOPX1.

RX_ORDEXT2

UCPD Rx Ordered Set Extension Register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												RXSOPX2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXSOPX2 rw

Toggle Fields

RXSOPX2

Bits 0-19: RXSOPX2.

IPVER

UCPD IP ID register

Offset: 0x3F4, reset: 0x00000010, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPVER r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPVER r

Toggle Fields

IPVER

Bits 0-31: IPVER.

IPID

UCPD IP ID register

Offset: 0x3F8, reset: 0x00150021, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IPID.

MID

UCPD IP ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields

IPID

Bits 0-31: IPID.

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

29/126 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD4_7				ADD0_3				RTOEN	ABRMOD		ABREN	MSBFIRST	TAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xC	BRR																	BRR_4_15												BRR_0_3
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1C	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NCF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2C	PRESC																													PRESCALER

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle Fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw				RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle Fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR_4_15 rw												BRR_0_3 rw

Toggle Fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle Fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle Fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle Fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle Fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

29/126 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD4_7				ADD0_3				RTOEN	ABRMOD		ABREN	MSBFIRST	TAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xC	BRR																	BRR_4_15												BRR_0_3
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1C	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NCF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2C	PRESC																													PRESCALER

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle Fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw				RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle Fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR_4_15 rw												BRR_0_3 rw

Toggle Fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle Fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle Fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle Fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle Fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler.

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

29/126 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD4_7				ADD0_3				RTOEN	ABRMOD		ABREN	MSBFIRST	TAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xC	BRR																	BRR_4_15												BRR_0_3
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1C	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NCF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2C	PRESC																													PRESCALER

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle Fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw				RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle Fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR_4_15 rw												BRR_0_3 rw

Toggle Fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle Fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle Fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle Fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle Fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler.

USART4

0x40004C00: Universal synchronous asynchronous receiver transmitter

29/126 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD4_7				ADD0_3				RTOEN	ABRMOD		ABREN	MSBFIRST	TAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xC	BRR																	BRR_4_15												BRR_0_3
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1C	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NCF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2C	PRESC																													PRESCALER

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle Fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw				RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle Fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle Fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR_4_15 rw												BRR_0_3 rw

Toggle Fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle Fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle Fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle Fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle Fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle Fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle Fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle Fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle Fields

PRESCALER

Bits 0-3: Clock prescaler.

WWDG

0x40002C00: System window watchdog

0/6 fields covered. Toggle Registers

Show register map

Offset	Name	13	9	7	6	0
0x0	CR			WDGA	T
0x4	CFR	WDGTB	EWI		W
0x8	SR					EWIF

CR

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDGA rw	T rw

Toggle Fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		WDGTB rw				EWI rw			W rw

Toggle Fields

W

Bits 0-6: 7-bit window value.

EWI

Bit 9: Early wakeup interrupt.

WDGTB

Bits 11-13: Timer base.

SR

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EWIF rw

Toggle Fields

EWIF

Bit 0: Early wakeup interrupt flag.